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CD74FCT273M96E4 PDF预览

CD74FCT273M96E4

更新时间: 2024-02-08 04:25:53
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 信息通信管理光电二极管逻辑集成电路触发器
页数 文件大小 规格书
9页 268K
描述
D Flip-Flop, FCT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, BICMOS, PDSO20, GREEN, PLASTIC, SOIC-20

CD74FCT273M96E4 技术参数

生命周期:Contact Manufacturer包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.6系列:FCT
JESD-30 代码:R-PDSO-G20长度:12.8 mm
逻辑集成电路类型:D FLIP-FLOP位数:8
功能数量:1端子数量:20
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):13 ns
座面最大高度:2.65 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:7.5 mm
最小 fmax:70 MHzBase Number Matches:1

CD74FCT273M96E4 数据手册

 浏览型号CD74FCT273M96E4的Datasheet PDF文件第2页浏览型号CD74FCT273M96E4的Datasheet PDF文件第3页浏览型号CD74FCT273M96E4的Datasheet PDF文件第4页浏览型号CD74FCT273M96E4的Datasheet PDF文件第5页浏览型号CD74FCT273M96E4的Datasheet PDF文件第6页浏览型号CD74FCT273M96E4的Datasheet PDF文件第7页 
CD74FCT273  
BiCMOS OCTAL D-TYPE FLIP-FLOP  
WITH RESET  
SCBS737A – JULY 2000 – REVISED JULY 2000  
E OR M PACKAGE  
(TOP VIEW)  
BiCMOS Technology With Low Quiescent  
Power  
Buffered Inputs  
CLR  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Direct Clear Input  
8Q  
8D  
7D  
7Q  
6Q  
6D  
48-mA Output Sink Current  
Output Voltage Swing Limited to 3.7 V  
Controlled Output Edge Rates  
Input/Output Isolation From V  
CC  
SCR Latch-Up-Resistant BiCMOS Process  
and Circuit Design  
13 5D  
12 5Q  
11  
GND  
CLK  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
– Pattern Generators  
Package Options Include Plastic  
Small-Outline (M) Package and Standard  
Plastic (E) DIP  
description  
The CD74FCT273 is a positive-edge-triggered, D-type flip-flop with a direct clear (CLR) input. This device uses  
a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that  
limits the output high level to two diode drops below V . This resultant lowering of output swing (0 V to 3.7 V)  
CC  
reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes V  
bounce and  
CC  
ground bounce and their effects during simultaneous output switching. The output configuration also enhances  
switching speed and is capable of sinking 48 mA.  
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the  
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not  
directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the  
D input has no effect at the output. All eight flip-flops are controlled by a common clock (CLK) and a common  
reset (CLR). The outputs are placed in a low state when CLR is taken low, independent of the CLK.  
The CD74FCT273 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
CLK  
D
X
H
L
CLR  
L
X
L
H
L
H
H
H
L
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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