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CD4053BKMS

更新时间: 2023-01-02 23:11:48
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
12页 149K
描述
Single-Ended Multiplexer, 3 Func, 2 Channel, CMOS, CDFP16

CD4053BKMS 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.46模拟集成电路 - 其他类型:SINGLE-ENDED MULTIPLEXER
JESD-30 代码:R-CDFP-F16标称负供电电压 (Vsup):
信道数量:2功能数量:3
端子数量:16最大通态电阻 (Ron):320 Ω
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装形状:RECTANGULAR
封装形式:FLATPACK认证状态:Not Qualified
最大供电电流 (Isup):0.025 mA标称供电电压 (Vsup):15 V
表面贴装:YES最长断开时间:608 ns
最长接通时间:972 ns技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子位置:DUALBase Number Matches:1

CD4053BKMS 数据手册

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CD4051BMS, CD4052BMS  
CD4053BMS  
CMOS Analog  
Multiplexers/Demultiplexers*  
December 1992  
Features  
Description  
• Logic Level Conversion  
CD4051BMS, CD4052BMS and CD4053BMS analog multi-  
plexers/demultiplexers are digitally controlled analog  
switches having low ON impedance and very low OFF leak-  
age current. Control of analog signals up to 20V peak-to-  
peak can be achieved by digital signal amplitudes of 4.5V to  
20V (if VDD-VSS = 3V, a VDD-VEE of up to 13V can be con-  
trolled; for VDD-VEE level differences above 13V, a VDD-  
VSS of at least 4.5V is required). For example, if VDD =  
+4.5V, VSS = 0, and VEE = -13.5V, analog signals from -  
13.5V to +4.5V can be controlled by digital inputs of 0 to 5V.  
These multiplexer circuits dissipate extremely low quiescent  
power over the full VDD-VSS and VDD-VEE supply voltage  
• High-Voltage Types (20V Rating)  
• CD4051BMS Signal 8-Channel  
• CD4052BMS Differential 4-Channel  
• CD4053BMS Triple 2-Channel  
• Wide Range of Digital and Analog Signal Levels:  
- Digital 3V to 20V  
- Analog to 20Vp-p  
• Low ON Resistance: 125(typ) Over 15Vp-p Signal  
Input Range for VDD - VEE = 15V  
ranges, independent of the logic state of the control signals.  
When a logic “1” is present at the inhibit input terminal all  
channels are off.  
• High OFF Resistance: Channel Leakage of ±100pA  
(typ) at VDD - VEE = 18V  
The CD4051BMS is a single 8 channel multiplexer having  
three binary control inputs, A, B, and C, and an inhibit input.  
The three binary signals select 1 of 8 channels to be turned  
on, and connect one of the 8 inputs to the output.  
• Logic Level Conversion:  
- Digital Addressing Signals of 3V to 20V (VDD - VSS  
= 3V to 20V)  
- Switch Analog Signals to 20Vp-p (VDD - VEE = 20V);  
See Introductory Text  
The CD4052BMS is a differential 4 channel multiplexer hav-  
ing two binary control inputs, A and B, and an inhibit input.  
The two binary input signals select 1 of 4 pairs of channels  
to be turned on and connect the analog inputs to the out-  
puts.  
• Matched Switch Characteristics: RON = 5(typ) for  
VDD - VEE = 15V  
• Very Low Quiescent Power Dissipation Under All Digi-  
tal Control Input and Supply Conditions: 0.2µW (typ)  
at VDD - VSS = VDD - VEE = 10V  
The CD4053BMS is a triple 2 channel multiplexer having  
three separate digital control inputs, A, B, and C, and an  
inhibit input. Each control input selects one of a pair of chan-  
nels which are connected in a single pole double-throw con-  
figuration.  
• Binary Address Decoding on Chip  
• 5V, 10V and 15V Parametric Ratings  
The CD4051BMS, CD4052BMS and CD4053BMS are supplied  
in these 16 lead outline packages:  
• 100% Tested for Quiescent Current at 20V  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
Braze Seal DIP  
*H4X  
H1E  
†H4T  
• Break-Before-Making Switching Eliminates Channel Frit Seal DIP  
Overlap  
Ceramic Flatpack  
*CD4051B Only  
H6W  
†CD4052B, CD4053 Only  
Applications  
• Analog and Digital Multiplexing and Demultiplexing  
• A/D and D/A Conversion  
• Signal Gating  
* When these devices are used as demultiplexers the “CHANNEL  
IN/OUT” terminals are the outputs and the “COMMON OUT/IN” ter-  
minals are the inputs.  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3316  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-937  

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