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CD4024BC PDF预览

CD4024BC

更新时间: 2024-09-29 22:54:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器
页数 文件大小 规格书
6页 59K
描述
7-Stage Ripple Carry Binary Counter

CD4024BC 数据手册

 浏览型号CD4024BC的Datasheet PDF文件第2页浏览型号CD4024BC的Datasheet PDF文件第3页浏览型号CD4024BC的Datasheet PDF文件第4页浏览型号CD4024BC的Datasheet PDF文件第5页浏览型号CD4024BC的Datasheet PDF文件第6页 
October 1987  
Revised April 2002  
CD4024BC  
7-Stage Ripple Carry Binary Counter  
General Description  
Features  
The CD4024BC is a 7-stage ripple-carry binary counter.  
Buffered outputs are externally available from stages 1  
through 7. The counter is reset to its logical “0” stage by a  
logical “1” on the reset input. The counter is advanced one  
count on the negative transition of each clock pulse.  
Wide supply voltage range: 3.0V to 15V  
High noise immunity: 0.45 VDD (typ.)  
Low power TTL compatibility: Fan out of 2 driving 74L  
or 1 driving 74LS  
High speed: 12 MHz (typ.)  
input pulse rate VDD VSS = 10V  
Fully static operation  
Ordering Code:  
Order Number Package Number  
Package Description  
CD4024BCM  
CD4024BCN  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Connection Diagram  
Top View  
© 2002 Fairchild Semiconductor Corporation  
DS005957  
www.fairchildsemi.com  

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