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CC2571 PDF预览

CC2571

更新时间: 2024-02-12 05:32:55
品牌 Logo 应用领域
德州仪器 - TI 射频
页数 文件大小 规格书
32页 764K
描述
1- and 8-Channel ANT? RF Network Processors

CC2571 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFN
包装说明:VQFN-40针数:40
Reach Compliance Code:compliantECCN代码:5A992.C
HTS代码:8542.31.00.01Factory Lead Time:6 weeks
风险等级:1.57Samacsys Confidence:4
Samacsys Status:Released2D Presentation:https://componentsearchengine.com/2D/0T/413716.1.1.png
Schematic Symbol:https://componentsearchengine.com/symbol.php?partID=413716PCB Footprint:https://componentsearchengine.com/footprint.php?partID=413716
3D View:https://componentsearchengine.com/viewer/3D.php?partID=413716Samacsys PartID:413716
Samacsys Image:https://componentsearchengine.com/Images/9/CC2571RHAT.jpgSamacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/1/CC2571RHAT.jpg
Samacsys Pin Count:41Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Quad Flat No-LeadSamacsys Footprint Name:RHA (S-PVQFN-N40)_1
Samacsys Released Date:2017-04-25 16:59:09Is Samacsys:N
总线兼容性:SPI; UART外部数据总线宽度:
JESD-30 代码:S-PQCC-N40JESD-609代码:e4
长度:6 mm湿度敏感等级:3
端子数量:40最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC40,.24SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:Other uPs/uCs/Peripheral ICs最大供电电压:3.6 V
最小供电电压:2 V标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

CC2571 数据手册

 浏览型号CC2571的Datasheet PDF文件第1页浏览型号CC2571的Datasheet PDF文件第2页浏览型号CC2571的Datasheet PDF文件第3页浏览型号CC2571的Datasheet PDF文件第5页浏览型号CC2571的Datasheet PDF文件第6页浏览型号CC2571的Datasheet PDF文件第7页 
CC2570  
CC2571  
SWRS095A FEBRUARY 2011REVISED MARCH 2011  
www.ti.com  
OSI Layer 7: Application  
Application written to run on the network  
OSI Layer 6: Presentation  
Data presentation and encryption  
OSI Layer 5: Session  
Inter-host communication  
User Defined  
ANT Protocol  
2.4 GHz Radio  
OSI Layer 4: Transport  
End to end connections and reliability  
OSI Layer 3: Network  
Path determination and IP (e.g. Logical addressing)  
OSI Layer 2: Datalink  
LLC and MAC sublayers (e.g. Physical addressing)  
OSI Layer 1: Physical  
Media, signaling and transmission  
M0210-01  
Figure 1. ANT OSI Layers  
The following sections offer a broad overview of the many features of ANT. For a detailed description of ANT and  
ANT+, please visit www.thisisant.com or www.ti.com/ant.  
ANT NODES  
An ANT node is any device that is capable of ANT wireless communications. It typically coconsists of an ANT  
chip, such as the TI CC2571, and an application host MCU, such as an MSP-430. The interface between the  
ANT chip and the host MCU is serial UART or SPI, depending on the requirements of the application. There is  
also a bit-synchronous serial protocol available, which may be fully implemented in software for very  
resource-constrained systems. The overhead required to interface to ANT is minimal, typically requiring less than  
1K of flash space to implement a simple API. A block diagram of an ANT node is depicted in Figure 2.  
Host MCU  
(e.g. MSP430)  
UART or SPI  
ANT  
(e.g. CC2571)  
M0211-01  
Figure 2. ANT Node  
ANT nodes may host multiple ANT channel endpoints, up to eight for the CC2571. Examples of ANT nodes  
include wireless watches, heart-rate straps, smart phones, glucose meters, blood-pressure monitors, and other  
sports and medical sensors.  
4
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Copyright © 2011, Texas Instruments Incorporated  
Product Folder Link(s): CC2570 CC2571  
 

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