Datasheet > CAT35C804ACC

CAT35C804ACC

更新时间： 2024-02-10 17:28:04

品牌	Logo	应用领域
CATALYST		可编程只读存储器电动程控只读存储器电可擦编程只读存储器内存集成电路
页数	文件大小	规格书
14页	88K
描述
EEPROM, 256X16, Serial, CMOS

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CAT35C804ACC 技术参数

生命周期：	Obsolete	包装说明：	, DIE OR CHIP
Reach Compliance Code：	unknown	风险等级：	5.84
备用内存宽度：	8	数据保留时间-最小值：	10
耐久性：	10000 Write/Erase Cycles	内存密度：	4096 bit
内存集成电路类型：	EEPROM	内存宽度：	16
字数：	256 words	字数代码：	256
最高工作温度：	70 °C	最低工作温度：
组织：	256X16	封装等效代码：	DIE OR CHIP
并行/串行：	SERIAL	电源：	5 V
认证状态：	Not Qualified	最大待机电流：	0.0001 A
子类别：	EEPROMs	最大压摆率：	0.003 mA
标称供电电压 (Vsup)：	5 V	技术：	CMOS
温度等级：	COMMERCIAL	写保护：	SOFTWARE
Base Number Matches：	1

CAT35C804ACC 数据手册

CAT35C804A

CLK

Preliminary

The System Clock is a TTL compatible input pin that

allows operation of the device at a specified frequency.

The CAT35C804A is designed with an internal divider to

producea9600baudoutputforaninputclockfrequency

of 4.9152 MHz.

The Data Output pin is a tri-state TTL compatible output.

It is normally in a high impedance state unless a READ

or an ENABLE BUSY instruction is executed. Following

thecompletionofa16-bitor8-bitdatastream, theoutput

will return to the high impedance state. During a pro-

gram/erase cycle, if the ENABLE BUSY instruction has

been previously executed, the output will stay LOW

while the device is BUSY, and it will be set HIGH when

the program/erase cycle is completed. DO will stay

HIGH until the completion of the next instruction’s op-

codeand,ifthenextinstructionisaREAD,DOwilloutput

the appropriate data at the end of the instruction. If the

ENABLE BUSY instruction has not been previously

executed,DOwillstayinahighimpedancestate.DOwill

The Data Input pin is TTL compatible and accepts data

and instructions in a serial format. Each byte must begin

with “0” as a start bit. The device will accept as many

bytes as an instruction requires, including both data and

address bytes. Extra bits will be disregarded if they are

“1”s and extra “0”s will be misinterpreted as the start bit

of the next instruction. An instruction error will cause the

device to abort operation and all I/O communication will

be terminated until a reset is received.

Figure 4. Program/Erase Timing (x8 Format)

OP CODE

OP0–OP7

ADDRESS

A8–A15

ADDRESS

A0–A7

DATA

D0–D7

HIGH-Z

(1)

BUSY

35C804 F07

Figure 5. Program/Erase Timing (x16 Format)

OP CODE

OP0–OP7

ADDRESS

A0–A7

DATA

D8–D15

D0–D7

(1)

HIGH-Z

BUSY

35C804 F08

Note:

(1) DO becomes low to indicate busy status if ENBSY was previously executed. If ENBSY was not previously executed, DO will be in the

High-Z condition.

Doc. No. 25043-00 2/98

1...3 4 567 8 9...14

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与CAT35C804ACC相关器件

型号	品牌	描述	获取价格	数据表
CAT35C804ACI	CATALYST	EEPROM, 256X16, Serial, CMOS	获取价格
CAT35C804ADI	ETC	Serial EEPROM	获取价格
CAT35C804AJATE13	CATALYST	4K-Bit Secure Access Serial E2PROM	获取价格
CAT35C804AJA-TE13	CATALYST	EEPROM, 512X8, Serial, CMOS, PDSO16, SOIC-16	获取价格
CAT35C804AJITE13	CATALYST	4K-Bit Secure Access Serial E2PROM	获取价格
CAT35C804AJI-TE13	ETC	Serial EEPROM	获取价格

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