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CAT24C082PA-25TE13 PDF预览

CAT24C082PA-25TE13

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
CATALYST 监控控制器可编程只读存储器
页数 文件大小 规格书
12页 89K
描述
Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer

CAT24C082PA-25TE13 数据手册

 浏览型号CAT24C082PA-25TE13的Datasheet PDF文件第3页浏览型号CAT24C082PA-25TE13的Datasheet PDF文件第4页浏览型号CAT24C082PA-25TE13的Datasheet PDF文件第5页浏览型号CAT24C082PA-25TE13的Datasheet PDF文件第7页浏览型号CAT24C082PA-25TE13的Datasheet PDF文件第8页浏览型号CAT24C082PA-25TE13的Datasheet PDF文件第9页 
CAT24CXX1/XX2  
Advanced  
Reset Threshold Voltage  
Hardware Data Protection  
From the factory the 24CXXX is offered in five different  
variations of reset threshold voltages. They are 4.50-  
4.75V, 4.25-4.50V, 3.00-3.15V, 2.85-3.00V and 2.55-  
2.70V. To provide added flexibility to design engineers  
using this product, the 24CXXX is designed with an  
additional feature of programming the reset threshold  
voltage. This allows the user to change the existing  
reset threshold voltage to one of the other four reset  
threshold voltages. Once the reset threshold voltage is  
selected it will not change even after cycling the power,  
unless the user uses the programmer to change the  
reset threshold voltage. However, the programming  
functionisavailableonlythroughthirdpartyprogrammer  
manufacturers. PleasecallCatalystforalistofprogram-  
mer manufacturers who support this function.  
The 24CXXX is designed with the following hardware  
data protection features to provide a high degree of data  
integrity.  
(1) The24CXXXfeaturesaWPpin.WhenWPpin istied  
high the entire memory array becomes write protected  
(read only).  
(2) The VCC sense provides write protection when VCC  
fallsbelowtheresetthresholdvalue(VTH). TheVCC lock  
out inhibits writes to the serial EEPROM whenever VCC  
falls below (power down) VTH or until VCC reaches the  
reset threshold (power up) VTH  
.
Figure 2. Bus Timing  
t
t
t
F
HIGH  
R
t
t
LOW  
LOW  
SCL  
t
t
HD:DAT  
SU:STA  
t
t
t
t
HD:STA  
SU:DAT  
SU:STO  
SDA IN  
BUF  
t
t
DH  
AA  
SDA OUT  
Figure 3. Write Cycle Timing  
SCL  
SDA  
8TH BIT  
BYTE n  
ACK  
t
WR  
STOP  
CONDITION  
START  
CONDITION  
ADDRESS  
Figure 4. Start/Stop Timing  
SDA  
SCL  
START BIT  
STOP BIT  
Doc. No. 25079-00 1/98 M-1  
6

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