Datasheet > CAT24C082JI-42

CAT24C082JI-42

更新时间： 2023-02-26 14:23:25

品牌	Logo	应用领域
CATALYST		可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
页数	文件大小	规格书
12页	73K
描述
EEPROM, 1KX8, Serial, CMOS, PDSO8

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CAT24C082JI-42 数据手册

Advanced Information

A.C. CHARACTERISTICS

CAT24CXX1/XX2

=2.7V to 6.0V unless otherwise specified.

Output Load is 1 TTL Gate and 100pF

Read & Write Cycle Limits

Symbol

Parameter

V_CC=2.7V - 6V

V_CC=4.5V - 5.5V

Min.

Max.

100

Min.

Max.

Units

kHz

F_SCL

T_I⁽¹⁾

Clock Frequency

400

200

Noise Suppression Time

200

Constant at SCL, SDA Inputs

t_AA

SCL Low to SDA Data Out

and ACK Out

3.5

µs

(1)

t_BUF

Time the Bus Must be Free Before

a New Transmission Can Start

4.7

1.2

t_HD:STA

t_LOW

Start Condition Hold Time

Clock Low Period

0.6

1.2

0.6

µs

4.7

t_HIGH

Clock High Period

t_SU:STA

Start Condition Setup Time

4.7

(for a Repeated Start Condition)

t_HD:DAT

t_SU:DAT

Data In Hold Time

µs

Data In Setup Time

(1)

t_R

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

Data Out Hold Time

0.3

(1)

t_F

300

t_SU:STO

t_DH

0.6

100

(1)(2)

Power-Up Timing

Symbol

Parameter

Max.

Units

t_PUR

t_PUW

Power-up to Read Operation

Power-up to Write Operation

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.

PUR

PUW

Write Cycle Limits

Symbol

Parameter

Min.

Typ.

Max

Units

t_WR

Write Cycle Time

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase

cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device

does not respond to its slave address.

Doc. No. 25079-00 8/99 M-1

1 234 5 6 7...12

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