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CAT24C082JA-28TE13

更新时间： 2024-01-27 04:11:17
品牌 Logo 应用领域
CATALYST 监控控制器可编程只读存储器
页数 文件大小 规格书
12页 89K
描述
Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer

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CAT24C082JA-28TE13 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP,
针数：8Reach Compliance Code：unknown
HTS代码：8542.31.00.01风险等级：5.92
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
长度：4.9 mm端子数量：8
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压：6 V最小供电电压：2.7 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：3.9 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT
Base Number Matches：1

CAT24C082JA-28TE13 数据手册

 浏览型号CAT24C082JA-28TE13的Datasheet PDF文件第4页浏览型号CAT24C082JA-28TE13的Datasheet PDF文件第5页浏览型号CAT24C082JA-28TE13的Datasheet PDF文件第6页浏览型号CAT24C082JA-28TE13的Datasheet PDF文件第8页浏览型号CAT24C082JA-28TE13的Datasheet PDF文件第9页浏览型号CAT24C082JA-28TE13的Datasheet PDF文件第10页 
Advanced  
CAT24CXX1/XX2  
FUNCTIONAL DESCRIPTION  
STOP Condition  
The CAT24CXXX supports the I2C Bus data transmis-  
sion protocol. This Inter-Integrated Circuit Bus protocol  
defines any device that sends data to the bus to be a  
transmitter and any device receiving data to be a re-  
ceiver. The transfer is controlled by the Master device  
which generates the serial clock and all START and  
STOP conditions for bus access. The CAT24CXXX  
operates as a Slave device. Both the Master device and  
Slave device can operate as either transmitter or re-  
ceiver, but the Master device controls which mode is  
activated.  
A LOW to HIGH transition of SDA when SCL is HIGH  
determinestheSTOPcondition.Alloperationsmustend  
with a STOP condition.  
DEVICE ADDRESSING  
The Master begins a transmission by sending a START  
condition. The Master sends the address of the particu-  
larslavedeviceitisrequesting. Thefourmostsignificant  
bits of the 8-bit slave address are fixed as 1010.  
The next three bits (Fig. 6) define memory addressing.  
For the 24C021/022, the three bits are don't care. For  
the 24C041/042, the next two bits are don't care and the  
third bit is the high order address bit. For the 24C081/  
082, the next bit is don't care and the successive bits  
define the higher order address bits. For the 24C161/  
162 the three bits define higher order bits.  
I2C BUS PROTOCOL  
The features of the I2C bus protocol are defined as  
follows:  
(1) Data transfer may be initiated only when the bus is  
not busy.  
The last bit of the slave address specifies whether a  
Read or Write operation is to be performed. When this  
bitissetto1, aReadoperationisselected, andwhenset  
to 0, a Write operation is selected.  
(2) During a data transfer, the data line must remain  
stable whenever the clock line is high. Any changes in  
thedatalinewhiletheclocklineishighwillbeinterpreted  
as a START or STOP condition.  
After the Master sends a START condition and the slave  
address byte, the CAT24CXXX monitors the bus and  
responds with an acknowledge (on the SDA line) when  
its address matches the transmitted slave address. The  
CAT24CXXX then performs a Read or Write operation  
depending on the state of the R/W bit.  
START Condition  
The START Condition precedes all commands to the  
device, and is defined as a HIGH to LOW transition of  
SDAwhenSCLisHIGH. TheCAT24CXXXmonitorsthe  
SDA and SCL lines and will not respond until this  
condition is met.  
Figure 5. Acknowledge Timing  
SCL FROM  
MASTER  
1
8
9
DATA OUTPUT  
FROM TRANSMITTER  
DATA OUTPUT  
FROM RECEIVER  
START  
ACKNOWLEDGE  
Figure 6. Slave Address Bits  
24C021/022  
1
0
1
0
X
X
X
X
R/W  
24C081/082  
24C161/162  
1
1
0
0
1
1
0
0
X
a9  
a8 R/W  
a8 R/W  
24C041/042  
a10 a9  
1
0
1
0
X
a8 R/W  
* 'X' Corresponds to Don't Care Bits (can be a zero or a one)  
** a8, a9 and a10 correspond to the address of the memory array address word.  
Doc. No. 25079-00 1/98 M-1  
7
1...45678910...12

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