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CAT24C022PA-28 PDF预览

CAT24C022PA-28

更新时间: 2024-02-16 08:54:18
品牌 Logo 应用领域
CATALYST 光电二极管外围集成电路
页数 文件大小 规格书
12页 74K
描述
Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8

CAT24C022PA-28 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:8Reach Compliance Code:unknown
HTS代码:8542.31.00.01风险等级:5.92
JESD-30 代码:R-PDIP-T8JESD-609代码:e0
长度:9.27 mm端子数量:8
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
认证状态:Not Qualified座面最大高度:4.57 mm
最大供电电压:6 V最小供电电压:2.7 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

CAT24C022PA-28 数据手册

 浏览型号CAT24C022PA-28的Datasheet PDF文件第2页浏览型号CAT24C022PA-28的Datasheet PDF文件第3页浏览型号CAT24C022PA-28的Datasheet PDF文件第4页浏览型号CAT24C022PA-28的Datasheet PDF文件第6页浏览型号CAT24C022PA-28的Datasheet PDF文件第7页浏览型号CAT24C022PA-28的Datasheet PDF文件第8页 
CAT24CXX1/XX2  
remain active until VCC reaches the VTH threshold and will  
PIN DESCRIPTIONS  
continuedrivingtheoutputsforapproximately200ms(tPURST  
)
WP:  
WRITE PROTECT  
after reaching VTH. After the tPURST timeout interval, the  
device will cease to drive the reset outputs. At this point the  
resetoutputswillbepulledupordownbytheirrespectivepull  
up/down resistors. During power-down, the RESET outputs  
will be active when VCC falls below VTH. The RESET outputs  
will be valid so long as VCC is >1.0V (VRVALID).  
If the pin is tied to VCC the entire memory array  
becomes Write Protected (READ only). When the pin  
is tied to GND or left floating normal read/write  
operations are allowed to the device.  
SCL: SERIAL CLOCK  
If there is no transition on the WDI for more than 1.6  
seconds, the watchdog timer times out.  
The RESET pins are I/Os; therefore, the CAT24CXXX can  
act as a signal conditioning circuit for an externally applied  
reset.Theinputsareedgetriggered;thatis,theRESETinput  
in the 24CXXX will initiate a reset timeout after detecting a  
lowtohightransitionandtheRESETinputintheCAT24CXXX  
will initiate a reset timeout after detecting a high to low  
transition.  
RESET/RESET: RESET I/O  
These are open drain pins and can be used as reset  
trigger inputs. By forcing a reset condition on the pins  
the device will initiate and maintain a reset condition  
for approximately 200ms. The RESET pin must be  
connected through a pull-down resistor, and the  
RESET pin must be connected through a pull-up  
resistor.  
Watchdog Timer  
TheWatchdogTimerprovidesanindependentprotectionfor  
microcontrollers. During a system failure, the CAT24CXXX  
will respond with a reset signal after a time-out interval of  
1.63 seconds for a lack of activity. The CAT24CXX1 is  
designedwiththeWatchdogTimerfeatureontheSDAinput.  
For the CAT24CXX1, if the microcontroller does not toggle  
the SDA input pin within 1.6 sectonds, the Watchdog Timer  
times out. This will generate a reset condition on reset  
outputs. The Watchdog Timer is cleared by any transition on  
WDI.  
SDA: SERIAL DATA ADDRESS  
The bidirectional serial data/address pin is used to  
transfer all data into and out of the device. The SDA  
pin is an open drain output and can be wire-ORed  
with other open drain or open collector outputs.  
DEVICE OPERATION  
Reset Controller Description  
As long as the reset signal is asserted, the Watchdog Timer  
will not count and will stay cleared. The CAT24CXX2 does  
not have a Watchdog.  
The CAT24CXXX precision RESET controller ensures  
correct system operation during brownout and power  
up/down conditions. It is configured with open drain  
RESET outputs. During power-up, the RESET outputs  
t
Figure 1. RESET Output Timing  
GLITCH  
V
TH  
V
RVALID  
V
CC  
t
RPD  
t
t
PURST  
PURST  
RESET  
t
RPD  
RESET  
Doc No. 3000, Rev. A  
5

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