Datasheet > CAT1163WI42

CAT1163WI42

更新时间： 2024-01-20 07:51:10

品牌	Logo	应用领域
安森美 - ONSEMI		光电二极管外围集成电路
页数	文件大小	规格书
14页	213K
描述
SPECIALTY MICROPROCESSOR CIRCUIT, PDSO8, SOIC-8

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技术参数
数据手册

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CAT1163WI42 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	8
Reach Compliance Code：	compliant	HTS代码：	8542.31.00.01
风险等级：	5.02	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
湿度敏感等级：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.75 mm	最大供电电压：	6 V
最小供电电压：	2.7 V	标称供电电压：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	3.9 mm	uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT
Base Number Matches：	1

CAT1163WI42 数据手册

CAT1163

FUNCTIONAL DESCRIPTION

The CAT1163 supports the I²C Bus data transmis–

sion protocol. This Inter-Integrated Circuit Bus proto–

col defines any device that sends data to the bus to

be a transmitter and any device receiving data to be a

receiver. The transfer is controlled by the Master

device which generates the serial clock and all

START and STOP conditions for bus access. Both the

Master device and Slave device can operate as either

transmitter or receiver, but the Master device controls

which mode is activated.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must

end with a STOP condition.

Device Addressing

The Master begins a transmission by sending a

START condition. The Master sends the address of

the particular slave device it is requesting. The four

most significant bits of the 8-bit slave address are

fixed as 1010.

I²C Bus Protocol

The features of the I²C bus protocol are defined as

follows:

The next three bits (Figure 6) define memory

addressing. For the CAT1163 the three bits define

higher order bits.

(1) Data transfer may be initiated only when the bus

is not busy.

The last bit of the slave address specifies whether a

Read or Write operation is to be performed. When this

bit is set to 1, a Read operation is selected, and when

set to 0, a Write operation is selected.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock line is

high will be interpreted as a START or STOP

condition.

After the Master sends a START condition and the

slave address byte, the CAT1163 monitors the bus

and responds with an acknowledge (on the SDA line)

when its address matches the transmitted slave

address. The CAT1163 then performs a Read or Write

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT1163 monitors the

SDA and SCL lines and will not respond until this

condition is met.

¯¯

operation depending on the R/W bit.

Figure 5. Acknowledge Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

Figure 6. Slave Address Bits

¯¯

R/W

CAT1163

a10 a9 a8

*a8, a9 and a10 correspond to the address of the memory array address word.

Characteristics subject to change without notice

Doc. No. MD-3003 Rev. I

1...4 5 678 9 10...14

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与CAT1163WI42相关器件

型号	品牌	描述	获取价格	数据表
CAT1163WI-42	CATALYST	Supervisory Circuits with I2C Serial Serial CMOS EEPROM, Precision Reset Controller and Wa	获取价格
CAT1163WI-42G	CATALYST	暂无描述	获取价格
CAT1163WI-42-G	ONSEMI	IC IC,SERIAL EEPROM,2KX8,CMOS,SOP,8PIN,PLASTIC, Microprocessor IC:Other	获取价格
CAT1163WI-42-GT2	CATALYST	Supervisory Circuits with I2C Serial Serial CMOS EEPROM, Precision Reset Controller and Wa	获取价格
CAT1163WI-42-GT3	CATALYST	Supervisory Circuits with I2C Serial Serial CMOS EEPROM, Precision Reset Controller and Wa	获取价格
CAT1163WI-42-GT3	ONSEMI	Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog	获取价格

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