Datasheet > CAT1163LI-25T2

CAT1163LI-25T2

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
CATALYST		监控控制器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
14页	151K
描述
Supervisory Circuits with I2C Serial Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer

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CAT1163LI-25T2 数据手册

CAT1163

STOP Condition

FUNCTIONAL DESCRIPTION

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must

end with a STOP condition.

The CAT1163 supports the I²C Bus data transmis–

sion protocol. This Inter-Integrated Circuit Bus proto–

col defines any device that sends data to the bus to

be a transmitter and any device receiving data to be a

receiver. The transfer is controlled by the Master

device which generates the serial clock and all

START and STOP conditions for bus access. Both the

Master device and Slave device can operate as either

transmitter or receiver, but the Master device controls

which mode is activated.

Device Addressing

The Master begins a transmission by sending a

START condition. The Master sends the address of

the particular slave device it is requesting. The four

most significant bits of the 8-bit slave address are

fixed as 1010.

The next three bits (Figure 6) define memory

addressing. For the CAT1163 the three bits define

higher order bits.

I²C BUS PROTOCOL

The features of the I²C bus protocol are defined as

follows:

The last bit of the slave address specifies whether a

Read or Write operation is to be performed. When this

bit is set to 1, a Read operation is selected, and when

set to 0, a Write operation is selected.

(1) Data transfer may be initiated only when the bus

is not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock line is

high will be interpreted as a START or STOP

condition.

After the Master sends a START condition and the

slave address byte, the CAT1163 monitors the bus

and responds with an acknowledge (on the SDA line)

when its address matches the transmitted slave

address. The CAT1163 then performs a Read or Write

START Condition

¯¯

operation depending on the R/W bit.

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT1163 monitors the

SDA and SCL lines and will not respond until this

condition is met.

Figure 5. Acknowledge Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

Figure 6. Slave Address Bits

¯¯

R/W

CAT1163

a10 a9 a8

*a8, a9 and a10 correspond to the address of the memory array address word.

Characteristics subject to change without notice

Doc. No. 3003 Rev. E

1...4 5 678 9 10...14

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与CAT1163LI-25T2相关器件

型号	品牌	描述	获取价格	数据表
CAT1163LI-25T3	CATALYST	Supervisory Circuits with I2C Serial Serial CMOS EEPROM, Precision Reset Controller and Wa	获取价格
CAT1163LI28	ONSEMI	SPECIALTY MICROPROCESSOR CIRCUIT, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-001, DIP-	获取价格
CAT1163LI-28	CATALYST	Supervisory Circuits with I2C Serial Serial CMOS EEPROM, Precision Reset Controller and Wa	获取价格
CAT1163LI-28	ONSEMI	IC SPECIALTY MICROPROCESSOR CIRCUIT, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-001, D	获取价格
CAT1163LI-28-G	CATALYST	Supervisory Circuits with I2C Serial Serial CMOS EEPROM, Precision Reset Controller and Wa	获取价格
CAT1163LI-28-G	ONSEMI	Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog	获取价格

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