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CAT1163LI-25T2 PDF预览

CAT1163LI-25T2

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
CATALYST 监控控制器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
14页 151K
描述
Supervisory Circuits with I2C Serial Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer

CAT1163LI-25T2 数据手册

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CAT1163  
up/down conditions. It is configured with open drain  
RESET outputs. During power-up, the RESET outputs  
remain active until VCC reaches the VTH threshold and  
will continue driving the outputs for approximately  
200ms (tPURST) after reaching VTH. After the tPURST  
timeout interval, the device will cease to drive the  
reset outputs. At this point the reset outputs will be  
pulled up or down by their respective pull up/down  
resistors. During power-down, the RESET outputs will  
PIN DESCRIPTION  
WDI: WATCHDOG INPUT  
If there is no transition on the WDI for more than 1.6  
seconds, the watchdog timer times out.  
WP: WRITE PROTECT  
If the pin is tied to VCC the entire memory array  
becomes Write Protected (READ only). When the pin  
is tied to GND or left floating normal read/write  
operations are allowed to the device.  
¯¯¯¯¯¯  
be active when VCC falls below VTH. The RESET  
outputs will be valid so long as VCC is >1.0V (VRVALID).  
The RESET pins are I/Os; therefore, the CAT1163  
can act as a signal conditioning circuit for an  
externally applied manual reset. The inputs are edge  
triggered; that is, the RESET input in the CAT1163 will  
initiate a reset timeout after detecting a low to high  
¯¯¯¯¯¯  
RESET/RESET: RESET I/O  
These are open drain pins and can be used as reset  
trigger inputs. By forcing a reset condition on the pins  
the device will initiate and maintain a reset condition.  
The RESET pin must be connected through a pull-  
¯¯¯¯¯¯  
transition and the RESET input will initiate a reset  
¯¯¯¯¯¯  
down resistor, and the RESET pin must be connected  
timeout after detecting a high to low transition.  
through a pull-up resistor.  
Watchdog Timer  
SDA: SERIAL DATA ADDRESS  
The Watchdog Timer provides an independent  
protection for microcontrollers. During a system  
failure, the CAT1163 will respond with a reset signal  
after a time-out interval of 1.6 seconds for a lack of  
activity. The CAT1163 is designed with the Watchdog  
Timer feature on the SDA input. If the microcontroller  
does not toggle the SDA input pin within 1.6 seconds,  
the Watchdog Timer times out. This will generate a  
reset condition on reset outputs. The Watchdog Timer  
is cleared by any transition on WDI.  
The bidirectional serial data/address pin is used to  
transfer all data into and out of the device. The SDA  
pin is an open drain output and can be wire-ORed  
with other open drain or open collector outputs.  
If there is no transition on the SDA for more than 1.6  
seconds, the watchdog timer times out.  
SCL: SERIAL CLOCK  
Serial clock input.  
As long as the reset signal is asserted, the Watchdog  
Timer will not count and will stay cleared.  
DEVICE OPERATION  
Reset Controller Description  
The CAT1163 precision RESET controller ensures  
correct system operation during brownout and power  
Figure 1. RESET Output Timing  
tGLITCH  
VTH  
V
RVALID  
VCC  
tRPD  
tPURST  
tPURST  
RESET  
tRPD  
RESET  
© 2007 Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
5
Doc. No. 3003 Rev. E  

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