Datasheet > CAT1021YI-30T2

CAT1021YI-30T2

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
CATALYST		监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
21页	278K
描述
Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer

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CAT1021YI-30T2 数据手册

CAT1021, CAT1022, CAT1023

RESET CIRCUIT AC CHARACTERISTICS

Symbol

t_PURST

t_RDP

Parameter

Test Conditions

Note 2

Min

Typ

Max

270

Units

µs

Power-Up Reset Timeout

V_THto RESET output Delay

V_CCGlitch Reject Pulse Width

130

200

Note 3

t_GLITCH

Note 4, 5

Note 1

MR Glitch Manual Reset Glitch Immunity

100

t_MRW

t_MRD

t_WD

MR Pulse Width

Note 1

µs

MR Input to RESET Output Delay

Watchdog Timeout

Note 1

µs

Note 1

1.0

1.6

2.1

sec

POWER-UP TIMING ^{(5), (6)}

Symbol

t_PUR

Parameter

Test Conditions

Min

Typ

Max

270

Units

Power-Up to Read Operation

Power-Up to Write Operation

t_PUW

AC TEST CONDITIONS

Parameter

Test Conditions

Input Pulse Voltages

Input Rise and Fall times

Input Reference Voltages

Output Reference Voltages

Output Load

0.2V_CCto 0.8V_CC

10ns

0.3V_CC, 0.7V_CC

0.5V_CC

Current Source: I_OL= 3mA; C_L= 100pF

RELIABILITY CHARACTERISTICS

Symbol Parameter

Reference Test Method

Min

Max

Units

(5)

N_END

Endurance

MIL-STD-883, Test Method 1033

MIL-STD-883, Test Method 1008

MIL-STD-883, Test Method 3015

JEDEC Standard 17

1,000,000

100

Cycles/Byte

Years

(5)

T_DR

Data Retention

ESD Susceptibility

Latch-Up

(5)

V_ZAP

2000

Volts

(5)(7)

I_LTH

100

Notes:

(1) Test Conditions according to “AC Test Conditions” table.

(2) Power-up, Input Reference Voltage V_CC= V_TH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table

(3) Power-Down, Input Reference Voltage V_CC= V_TH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table

(4) V_CCGlitch Reference Voltage = V_THmin; Based on characterization data

(5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

(6) t_PURand t_PUWare the delays required from the time V_CCis stable until the specified memory operation can be initiated.

(7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V_CC+ 1V.

Doc. No. 3009 Rev. L

Characteristics subject to change without notice

1...3 4 567 8 9...21

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