Datasheet > CAT1021YI-28T3

CAT1021YI-28T3

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
CATALYST		监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
21页	278K
描述
Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer

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数据手册

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CAT1021YI-28T3 数据手册

CAT1021, CAT1022, CAT1023

CAPACITANCE

T_A= 25ºC, f = 1.0MHz, V_CC= 5V

Symbol Test

Test Conditions

V_OUT= 0V

Max

Units

(1)

C_OUT

Output Capacitance

Input Capacitance

(1)

C_IN

V_IN= 0V

AC CHARACTERISTICS

_CC= 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.

Memory Read & Write Cycle⁽²⁾

Symbol Parameter

Min

Max

400

100

Units

kHz

f_SCL

t_SP

t_LOW

t_HIGH

Clock Frequency

Input Filter Spike Suppression (SDA, SCL)

Clock Low Period

1.3

0.6

µs

Clock High Period

µs

(1)

t_R

SDA and SCL Rise Time

300

(1)

t_F

SDA and SCL Fall Time

t_{HD; STA}

t_{SU; STA}

t_{HD; DAT}

t_{SU; DAT}

t_{SU; STO}

t_AA

Start Condition Hold Time

0.6

µs

Start Condition Setup Time (for a Repeated Start)

Data Input Hold Time

µs

Data Input Setup Time

100

0.6

Stop Condition Setup Time

SCL Low to Data Out Valid

Data Out Hold Time

µs

900

t_DH

(1)

t_BUF

Time the Bus must be Free Before a New Transmission Can Start

Write Cycle Time (Byte or Page)

1.3

µs

(3)

t_WC

Notes:

(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

(2) Test Conditions according to “AC Test Conditions” table.

(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the

write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.

Characteristics subject to change without notice

Doc. No. 3009 Rev. L

1 2 3 456 7 8...21

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