Datasheet > C9837AT

C9837AT

更新时间： 2024-02-10 22:15:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管外围集成电路
页数	文件大小	规格书
20页	319K
描述
Processor Specific Clock Generator, CMOS, PDSO48, TSSOP-48

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C9837AT 技术参数

生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.8
JESD-30 代码：	R-PDSO-G48	JESD-609代码：	e0
长度：	12.5 mm	端子数量：	48
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：	Not Qualified	座面最大高度：	1.2 mm
表面贴装：	YES	技术：	CMOS
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
宽度：	6.1 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

+/+…when timing is critical

C9837

Low EMI Clock Generator for Intel Mobile 133MHz/2 SO-DIMM Chipset Systems

Preliminary

PCI_STP# Timing

PCI_STP# is an input to the clock generator and is made synchronous to the clock driver PCI_F output. It is used to turn

off the PCI clocks for low power operation. PCI clocks are stopped in a low state and started such that a full high pulse

width is guaranteed. ONLY one rising edge of PCI_F occurs after the clock control logic switched for the PCI outputs to

become enabled/disabled.

PCI_STP# Timing Diagram

PCI_F

Tsu

PCI_STP#

PCI(1:6)

CPU_STP#

PD#

(High)

Figure 3

Notes:

1. All internal timing is referenced to the CPU clock.

2. PCI_STP# signal is an input signal which must be made synchronous to PCI_F output.

3. All other clocks continue to run undisturbed.

4. PD# is understood to be in a high state.

5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.0

3/30/2000

Page 6 of 20

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