Datasheet > C9837AT

C9837AT

更新时间： 2024-02-20 14:27:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管外围集成电路
页数	文件大小	规格书
20页	319K
描述
Processor Specific Clock Generator, CMOS, PDSO48, TSSOP-48

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技术参数
数据手册

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C9837AT 技术参数

生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.8
JESD-30 代码：	R-PDSO-G48	JESD-609代码：	e0
长度：	12.5 mm	端子数量：	48
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：	Not Qualified	座面最大高度：	1.2 mm
表面贴装：	YES	技术：	CMOS
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
宽度：	6.1 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

C9837AT 数据手册

+/+…when timing is critical

C9837

Low EMI Clock Generator for Intel Mobile 133MHz/2 SO-DIMM Chipset Systems

Preliminary

Power Management Timing

0ns

10ns

20ns

30ns

40ns

50ns

60ns

CPU 100 MHz

3V66 66 MHz

PCI 33 MHz

IOAPIC 33 MHz

PD#

SDRAM 100 MHz

REF 14.3 MHz

48M (0,1)

Figure 1

Power Management Current

Maximum 2.5 Volt Current

Consumption (VDDC = VDDI =

2.625V)

Maximum 3.3 Volt Current Consumption

(VDD = AVDD = VDDS = 3.465V)

CONDITIONS

Power down (PD# = LOW)

CPU=66MHz @ max loads

CPU=100MHz @ max loads

CPU=133MHz @ max loads

< 1mA

60mA (Preliminary)

75mA (Preliminary)

160mA (Preliminary)

90mA (Preliminary)

Table 3

When exiting the power down mode, the application must supply power to the VDD pins a minimum of 200ms before

releasing the PD# pin high to insure that an orderly startup will occur and that the initial clocks that the device produces

are full and correctly compliant with data sheet specified phase relationships.

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,

MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571

http://www.imicorp.com

Rev 1.0

3/30/2000

Page 4 of 20

1 2 345 6 7...20

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