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C9835CYT

更新时间: 2024-02-10 01:32:49
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器
页数 文件大小 规格书
18页 345K
描述
Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems

C9835CYT 技术参数

生命周期:Transferred零件包装代码:SSOP
包装说明:,针数:56
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.51
JESD-30 代码:R-PDSO-G56端子数量:56
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
表面贴装:YES技术:CMOS
端子形式:GULL WING端子位置:DUAL
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

C9835CYT 数据手册

 浏览型号C9835CYT的Datasheet PDF文件第2页浏览型号C9835CYT的Datasheet PDF文件第3页浏览型号C9835CYT的Datasheet PDF文件第4页浏览型号C9835CYT的Datasheet PDF文件第6页浏览型号C9835CYT的Datasheet PDF文件第7页浏览型号C9835CYT的Datasheet PDF文件第8页 
C9835  
CPU(1,2)  
PCI_F  
Tsu  
Tsu  
CPU_STP#  
CPU0  
PCI_STP#  
(High)  
(High)  
PWR_DWN#  
Figure 2. CPU_STP Timing Diagram  
PCI_F  
Tsu  
Tsu  
PCI_STP#  
PCI(1:6)  
CPU_STP#  
PD#  
(High)  
(High)  
Figure 3. PCI_STP# Timing Diagram[[10,11,12,13,14]  
Note:  
10. All the internal timing is referenced to the CPU clock  
11. PCI_STP# signal is an input signal that must be made synchronous to PCI_F output.  
12. All other clocks continue to run undisturbed.  
13. PD# is understood to in a high state.  
14. Diagrams shown with respect to 133 MHz. Similar operation when CPU is 100 MHz  
Document #: 38-07303 Rev. **  
Page 5 of 18  

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