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C9835CYT

更新时间： 2024-02-11 18:47:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器
页数 文件大小 规格书
18页 345K
描述
Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems

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C9835CYT 技术参数

生命周期：Transferred零件包装代码：SSOP
包装说明：,针数：56
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.51
JESD-30 代码：R-PDSO-G56端子数量：56
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
表面贴装：YES技术：CMOS
端子形式：GULL WING端子位置：DUAL
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

C9835CYT 数据手册

 浏览型号C9835CYT的Datasheet PDF文件第1页浏览型号C9835CYT的Datasheet PDF文件第2页浏览型号C9835CYT的Datasheet PDF文件第4页浏览型号C9835CYT的Datasheet PDF文件第5页浏览型号C9835CYT的Datasheet PDF文件第6页浏览型号C9835CYT的Datasheet PDF文件第7页 
C9835  
Table 2. Expanded Frequency Selection (MHz)[4, 5, 6]  
SDRAM(0:5),  
DCLK  
PCI_F,  
3V66(0:2) PCI(1:6)  
TEST# ESEL ESEL  
SEL  
SEL CPU(0:2)  
Notes  
0% extension  
(Default)  
1
0
0
0
0
66.7  
100[6]  
66.6  
33  
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100  
133.3  
133.3  
70  
100[6]  
133.3  
100[6]  
105[6]  
105[6]  
140  
105[6]  
110[6]  
110[6]  
146.7  
110[6]  
120[6]  
120[6]  
160  
66.6  
66.6  
66.6  
70  
33  
33  
33  
35  
5% extension  
10% extension  
20% extension  
105  
70  
35  
140  
70  
35  
140  
70  
35  
73.3  
110  
73.3  
73.3  
73.3  
73.3  
80  
36.6  
36.6  
36.6  
36.6  
40  
146.7  
146.7  
80  
120  
80  
40  
160  
80  
40  
160  
120[6]  
80  
40  
Power Management Functions  
Power management on this device is controlled by the PD#,  
CPU_STP# and PCI_STP# pins. When PD# is high (default)  
the device is in normal running mode and all signals are active.  
in a low state on their next high-to-low transition. The REF and  
USB clocks are stopped in a low state as soon as possible.  
When in power down (and before power is removed), all  
outputs are synchronously stopped in a low state (see  
Figure 1), all PLLs are shut off, and the crystal oscillator is  
disabled. When the device is shutdown, the I²C function is  
also disabled.  
The PD# signal is used to bring all clocks to a low level in an  
orderly fashion prior to power (all except AVDD) being  
removed from the part. When PD# is asserted (forced) low, the  
device transitions to a shutdown (power down) mode and all  
power supplies (3.3V and 2.5V except for AVDD) may then be  
removed. When PD# is sampled low by two consecutive rising  
edges of the CPU clock, then all affected clocks are stopped  
At power-up, using the PD# select pin, all clocks are started in  
such a manner as to guarantee a glitch-free operation, no  
partial clock pulses.  
Notes:  
4. Extended frequencies are only available via SMBUS interface. They are accessable via SMBUS Byte 5 bits 0,1.  
5. 48M(0,1) clocks are constant at 48 MHz and REF is constant at 14.31818 MHz for all table selections.  
6. Will be set to 133 MHz and boosted accordingly, when Byte3,Bit 0 is set to logic 1.  
Document #: 38-07303 Rev. **  
Page 3 of 18  
1234567...18

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