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C9530CT PDF预览

C9530CT

更新时间: 2024-02-08 13:12:02
品牌 Logo 应用领域
其他 - ETC 晶体时钟发生器外围集成电路光电二极管
页数 文件大小 规格书
14页 182K
描述
CPU SYSTEM CLOCK GENERATOR|CMOS|TSSOP|48PIN|PLASTIC

C9530CT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-48
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.88JESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:12.5 mm
端子数量:48最高工作温度:70 °C
最低工作温度:最大输出时钟频率:133.33 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V主时钟/晶体标称频率:33.33 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Clock Generators最大压摆率:30 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.1 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

C9530CT 数据手册

 浏览型号C9530CT的Datasheet PDF文件第2页浏览型号C9530CT的Datasheet PDF文件第3页浏览型号C9530CT的Datasheet PDF文件第4页浏览型号C9530CT的Datasheet PDF文件第5页浏览型号C9530CT的Datasheet PDF文件第6页浏览型号C9530CT的Datasheet PDF文件第7页 
APPROVED PRODUCT  
C9530  
PCIX I/O System Clock Generator With EMI Control Features  
Product Features  
Test Mode Logic Table  
Dedicated clock buffer power pins for reduced  
noise, crosstalk and jitter  
INPUT PINS  
OUTPUT PINS  
OEA  
OEB  
SA1  
SB1  
LOW  
LOW  
HIGH  
HIGH  
X
SA0  
SB0  
CLKA(0:4)  
REF  
Buffer XIN Reference clock output  
CLKB(0:4)  
XIN  
Input clock frequency 33.3 MHz  
Reference may be a clock or a crystal  
HIGH  
HIGH  
HIGH  
HIGH  
LOW  
LOW  
XIN  
XIN  
HIGH  
LOW  
HIGH  
X
2 * XIN  
3 * XIN  
4 * XIN  
Tri-State  
XIN  
Output frequencies of 33.3, 66.6, 100 and 133.3  
MHz selectable (PCIX requirements)  
XIN  
Tri-State  
Output grouped in two banks of 5 clocks each.  
SMBus clock control interface for individual clock  
disabling, SSCG control and individual bank  
frequency selection  
Note: A and B banks have separate frequency select  
and output enable controls. XIN is the frequency of the  
clock on the device’s XIN pin. OEA or OEB will tristate  
REF.  
Output clock duty cycle is 50% (± 5%)  
<250 pS skew between output clocks within a bank  
Output jitter <250 pSec. (175pSec with all outputs  
at the same frequency)  
Spread Spectrum feature for reduced EMI  
OE pins for separate output bank enable control  
and testability  
Pin Configuration  
48  
REF  
VDD  
1
SDATA  
SCLK  
VDD  
2
47  
46  
45  
44  
48 Pin SSOP and TSSOP package  
XIN  
3
XOUT  
VSS  
4
VSS  
Block Diagram  
5
VDD  
SA0  
6
SB0  
43  
42  
41  
SA1  
7
SB1  
VSS  
8
VSS  
AGOOD#  
CLKA0  
CLKA1  
VDDA  
CLKA2  
VSS  
9
CLKB0  
CLKB1  
VDDB  
CLKB2  
VSS  
40  
39  
38  
37  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
SSCG  
Logic  
CLKA0  
CLKA1  
SSCG#  
/N  
1
0
36  
35  
34  
33  
CLKA2  
CLKA3  
CLKA4  
VDDA  
CLKA3  
CLKA4  
VSS  
VDDB  
CLKB3  
CLKB4  
VSS  
XIN  
OEA  
32  
31  
30  
29  
28  
CLKB0  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
OEB  
BGOOD#  
REF  
AGOOD#  
VSS  
BGOOD#  
AVDD  
AVDD  
VSS  
XOUT  
0
1
IA0  
IA1  
/N  
SDATA  
27  
26  
25  
IA2  
SSCG#  
VSS  
AVDD  
OEA  
SCLK  
I2C  
Control  
Logic  
OEB  
IA(0:2)  
SA(0,1)  
SB(0,1)  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07033 Rev. **  
5/1/2000  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 1 of 14  

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