C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
19.1. Timer 0 and Timer 1 ............................................................................................................................136
Figure 19.1. T0 Mode 0 Block Diagram........................................................................................................137
Figure 19.2. T0 Mode 2 Block Diagram........................................................................................................138
Figure 19.3. T0 Mode 3 Block Diagram........................................................................................................139
Figure 19.4. TCON: Timer Control Register .................................................................................................140
Figure 19.5. TMOD: Timer Mode Register ...................................................................................................141
Figure 19.6. CKCON: Clock Control Register...............................................................................................142
Figure 19.7. TL0: Timer 0 Low Byte.............................................................................................................143
Figure 19.8. TL1: Timer 1 Low Byte.............................................................................................................143
Figure 19.9. TH0: Timer 0 High Byte............................................................................................................143
Figure 19.10. TH1: Timer 1 High Byte..........................................................................................................143
19.2. Timer 2.................................................................................................................................................144
Figure 19.11. T2 Mode 0 Block Diagram......................................................................................................145
Figure 19.12. T2 Mode 1 Block Diagram......................................................................................................146
Figure 19.13. T2 Mode 2 Block Diagram......................................................................................................147
Figure 19.14. T2CON: Timer 2 Control Register ..........................................................................................148
Figure 19.15. RCAP2L: Timer 2 Capture Register Low Byte .......................................................................149
Figure 19.16. RCAP2H: Timer 2 Capture Register High Byte ......................................................................149
Figure 19.17. TL2: Timer 2 Low Byte...........................................................................................................149
Figure 19.18. TH2: Timer 2 High Byte..........................................................................................................149
19.3. Timer 3.................................................................................................................................................150
Figure 19.19. Timer 3 Block Diagram...........................................................................................................150
Figure 19.20. TMR3CN: Timer 3 Control Register.......................................................................................150
Figure 19.21. TMR3RLL: Timer 3 Reload Register Low Byte .....................................................................151
Figure 19.22. TMR3RLH: Timer 3 Reload Register High Byte ....................................................................151
Figure 19.23. TMR3L: Timer 3 Low Byte.....................................................................................................151
Figure 19.24. TMR3H: Timer 3 High Byte....................................................................................................151
20. PROGRAMMABLE COUNTER ARRAY ...................................................................152
Figure 20.1. PCA Block Diagram ..................................................................................................................152
20.1. Capture/Compare Modules...................................................................................................................153
Table 20.1. PCA0CPM Register Settings for PCA Capture/Compare Modules ............................................153
Figure 20.2. PCA Interrupt Block Diagram ...................................................................................................153
Figure 20.3. PCA Capture Mode Diagram.....................................................................................................154
Figure 20.4. PCA Software Timer Mode Diagram.........................................................................................155
Figure 20.5. PCA High Speed Output Mode Diagram...................................................................................155
Figure 20.6. PCA PWM Mode Diagram........................................................................................................156
20.2. PCA Counter/Timer .............................................................................................................................157
Table 20.2. PCA Timebase Input Options .....................................................................................................157
Figure 20.7. PCA Counter/Timer Block Diagram..........................................................................................157
20.3. Register Descriptions for PCA.............................................................................................................158
Figure 20.8. PCA0CN: PCA Control Register................................................................................................158
Figure 20.9. PCA0MD: PCA Mode Register.................................................................................................159
Figure 20.10. PCA0CPMn: PCA Capture/Compare Registers.......................................................................160
Figure 20.11. PCA0L: PCA Counter/Timer Low Byte ..................................................................................161
Figure 20.12. PCA0H: PCA Counter/Timer High Byte.................................................................................161
Figure 20.13. PCA0CPLn: PCA Capture Module Low Byte.........................................................................161
Figure 20.14. PCA0CPHn: PCA Capture Module High Byte........................................................................161
21. JTAG (IEEE 1149.1) .......................................................................................................162
Figure 21.1. IR: JTAG Instruction Register...................................................................................................162
21.1. Boundary Scan .....................................................................................................................................163
Table 21.1. Boundary Data Register Bit Definitions......................................................................................163
Figure 21.2. DEVICEID: JTAG Device ID Register.....................................................................................164
21.2. Flash Programming Commands ...........................................................................................................165
Figure 21.3. FLASHCON: JTAG Flash Control Register..............................................................................166
Page 6
CYGNAL Integrated Products, Inc. 2001
4.2001; Rev. 1.3
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