Datasheet > C1632C101M4GAC

C1632C101M4GAC

更新时间： 2023-01-03 04:29:06

品牌	Logo	应用领域
基美 - KEMET		/
页数	文件大小	规格书
2页	776K
描述
ISOLATED C NETWORK, 16V, C0G, 0.0001uF, SURFACE MOUNT, CHIP-8, CHIP, ROHS COMPLIANT

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数据手册

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C1632C101M4GAC 数据手册

CERAMIC CAPACITOR ARRAY

FEATURES

• Four individual capacitors inside

• Easier to handle and solder than 4 smaller chips

one 1206 monolithic structure

• Saves board and inventory space

• One placement instead of four - less costly

• Tape and reel per EIA 481-1

• RoHS Compliant

CAPACITOR OUTLINE DRAWING

BW1

P/2

Ref

TABLE 1

EIA DIMENSIONS – MILLIMETERS (INCHES)

Length

Width

Thickness

T (max.)

Bandwidth

BW1

Pitch

Size

Code

1632

3.2 (0.126)

0.2 (0.008)

1.6 (.063)

0.2 (.008)

0.7 - 1.35

(0.027 - 0.053)

0.40 (0.016)

0.2 (0.008) (0.004 - 0.020)

0.1 - 0.5

0.8 (0.031)

0.1 (0.004)

Notes:

1. Metric is controlling - English for reference only.

2. Pitch (P) tolerances are non-cumulative along the package.

3. Thickness (T) depends on capacitance.

CERAMIC ARRAY ORDERING INFORMATION

1632

103

CERAMIC

EIA SIZE CODE

Ceramic chip array

END METALLIZATION

C-Standard

(Tin-plated nickel barrier)

FAILURE RATE LEVEL

SPECIFICATION

C - Standard

A- Not Applicable

CAPACITANCE CODE

Expressed in Picofarads (pF)

TEMPERATURE CHARACTERISTIC

Designated by Capacitance

Change Over Temperature Range

G – C0G (NP0) ( 30 PPM/°C)

First two digits represent significant figures.

Third digit specifies number of zeros. (Use 9

for 1.0 thru 9.9pF. (Example: 2.2pF = 229

R – X7R ( 15%)

VOLTAGE

5 = 50v; 3 = 25v; 4 = 16v; 8=10v

CAPACITANCE TOLERANCE

K – 10%: M – 20% Standard Tolerances

Contact factory for any special requirements.

©KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300

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