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BUS-61571-300Q PDF预览

BUS-61571-300Q

更新时间: 2024-01-13 17:00:35
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
4页 50K
描述
MIL-STD-1553B NOTICE 2 ADVANCED INTEGRATED MUX HYBRIDS WITH ENHANCED RT FEATURES (AIM-HYer)

BUS-61571-300Q 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP,针数:82
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.84地址总线宽度:16
边界扫描:NO通信协议:MIL-STD-1553B
数据编码/解码方法:NRZ最大数据传输速率:0.125 MBps
外部数据总线宽度:16JESD-30 代码:R-XDFP-F82
低功率模式:NO串行 I/O 数:2
端子数量:82最高工作温度:70 °C
最低工作温度:封装主体材料:UNSPECIFIED
封装代码:DFP封装形状:RECTANGULAR
封装形式:FLATPACK认证状态:Not Qualified
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:FLAT端子位置:DUAL
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553Base Number Matches:1

BUS-61571-300Q 数据手册

 浏览型号BUS-61571-300Q的Datasheet PDF文件第2页浏览型号BUS-61571-300Q的Datasheet PDF文件第3页浏览型号BUS-61571-300Q的Datasheet PDF文件第4页 
BUS -6 1 5 5 9 S ERIES  
MIL-S TD-1 5 5 3 B NOTICE 2  
ADVANCED INTEGRATED MUX HYBRIDS  
WITH ENHANCED RT FEATURES (AIM-HYe r)  
DESCRIPTION  
FEATURES  
DDC’s BUS-61559 series of Advanced buffers to provide a direct interface to  
Integrated Mux Hybrids with enhanced a host processor bus. Alternatively,  
RT Features (AIM-HY’er) comprise a the buffers may be operated in a fully  
complete interface between a micro- transparent mode in order to interface  
Complete Integrated 1553B  
Notice 2 Interface Terminal  
processor and  
a MIL-STD-1553B to up to 64K words of external shared  
Functlonal Superset of BUS-  
61553 AlM-HYSeries  
Notice bus, implementing Bus RAM and/or connect directly to a com-  
2
Controller (BC), Remote Terminal (RX, ponent set supporting the 20 MHz  
and Monitor Terminal (MT) modes. STANAG-3910 bus.  
Internal Address and Data  
Buffers for Dlrect Interface to  
Processor Bus  
Packaged in a single 78-pin DIP or  
The memory management scheme  
82-pin flat package the BUS-61559  
for RT mode prevails an option for  
series contains dual low-power trans-  
separation of broadcast data, in com-  
ceivers and encoder/decoders, com-  
pliance with 1553B Notice 2. A circu-  
plete BC/RT/MT protocol logic, memory  
lar buffer option for RT message data  
management and interrupt logic, 8K x 16  
blocks offloads the host processor for  
of shared static RAM, and a direct,  
bulk data transfer applications.  
RT Subaddress Circular Buffers  
to Support Bulk Data Transfers  
buffered interface to a host processor bus.  
Optlonal Separatlon of  
RT Broadcast Data  
Another feature besides those listed  
to the right, is a transmitter inhibit con-  
trol for the individual bus channels.  
The BUS-61559 includes a number of  
advanced features in support of  
MIL-STD-1553B Notice 2 and STANAG  
Internal Interrupt Status and  
Time Tag Registers  
3838. Other salient features of the  
BUS-61559 serve to provide the bene-  
fits of reduced board space require-  
ments enhanced software flexibility,  
and reduced host processor overhead  
The BUS-61559 series hybrids oper-  
ate over the full military temperature  
range of -55 to +125”C and MIL-PRF-  
38534 processing is available. The  
hybrids are ideal for demanding mili-  
tary and industrial microprocessor-to-  
1553 applications  
Internal ST Command  
Illegalization  
The BUS-61559 contains internal  
address latches and bidirectional data  
MIL-PRF-38534 Processing  
Available  
(ILLEGALIZATION  
ILLENA  
ILLEGALLIZATION  
LOGIC  
ENABLE)  
8K x 16  
DUAL  
PORT  
RAM  
CLK IN (16MHz)  
BUS-25679  
8
7
5
4
1
LOW-POWER  
TRANSCEIVER  
A
2
3
DUAL  
TX_INH_A  
ENCODER/  
DECODER  
BC/RT/MT  
PROTOCOL  
DATA  
BUFFERS*  
(PROCESSOR  
DATA)  
MEMORY DATA  
D15-D  
BUS-25679  
8
7
5
4
1
(PROCESSOR  
ADDRESS)  
LOW-POWER  
TRANSCEIVER  
A
A15-A  
2
ADDRESS  
LATCHES/  
BUFFERS*  
MEMORY ADDRESS  
3
(ADDRESS  
LATCH  
CONTROL)  
ADDR_LAT  
TX_INH_A  
TRANSPARENT/BUFFERED, MSTCLR,  
STRBD, SELECT, MEM/REG, RD/WR  
RTAD 4- , RTADP  
BRO_ENA  
RTFAIL  
(RT ADDRESS)  
(PROCESSOR  
CONTROL)  
MEMORY  
MANAGEMENT,  
SHARED  
IOEN, READYD  
INT  
(BROADCAST  
ENABLE)  
(INTERRUPT  
REQUEST)  
RAM/  
MEMEN-OUT,MEMWR, MEMOE  
MEMENA-IN  
(MEMORY  
CONTROL)  
PROCESSOR  
INTERFACE,  
INTERRUPT  
LOGIC  
(RTFAIL,  
RTFLAG)  
RTFLAG  
(SUBSYSTEM  
FLAG)  
SSFLAG  
(BROADCAST,  
MESSAGE  
TIMING, DATA  
(TIME TAG  
CLOCK)  
TAGCLK  
BCSTRCV, CMD_STR, TXDTA_STR  
RXDTA_STR, MSG_ERR, INCMD  
STROBE AND ERROR  
INDICATORS)  
BU-61559 BLOCK DIAGRAM  
© 1990, 1999 Data Device Corporation  

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