BU97960MUV
MAX 120 Segments (SEG15×COM8)
Function Description – continued
Command Transfer Method
Issue Slave Address (“01111100”) after generate “START condition”.
The 1st byte after Slave Address always becomes command input.
MSB (“Command or Data judgement bit”) of command decides next data is Command or Display Data.
When set “Command or Data judgement bit”=“1”, next byte will be command.
When set “Command or Data judgement bit”=“0”, next byte data is Display Data.
…
A
1 Command
1 Command
A
1
S
A
Display Data
P
Slave Address
Command
A
0
Command
A 0
A
It cannot accept input command once it enters into Display Data transfer state.
In order to input command again, it is necessary to generate “START condition”.
If “START condition” or “STOP condition” is sent in the middle of command transmission, the command will be cancelled.
If Slave Address is continuously sent following “START condition”, it remains in command input state.
“Slave Address” must be sent right after the “START condition”.
When Slave Address cannot be recognized in the first data transmission, no Acknowledge bit is generated and next
transmission will be invalid. When the data is in invalid status, if “START condition” is transmitted again, it will return to valid
status.
Consider the MPU interface characteristic such as Input rise time and Setup/Hold time when transferring command and data
(Refer to MPU Interface Characteristics).
Write Display Data and Transfer Method
BU97960MUV enters “Write Mode” when Write Mode or Read Mode judgement bit of Slave Address is “0”
BU97960MUV has Display Data RAM (DDRAM) of 15×8=120bits.
The relationship between data input and Display Data, DDRAM data and the address are as follows.
Slave Address
Command
0 000000
…
S
i
j
k
l
n
m o
A
0111110
0
A
p
A
a
b
c
d
e
f
g
h
A
P
R/W=0 (Write Mode)
Display Data
In 1/8 Duty Mode
8-bit data is stored in DDRAM. ADSET command specifies the address to be written, and address is automatically
incremented in every 8-bit data.
Data can be continuously written in DDRAM by transmitting data continuously.
DDRAM Address
0h
a
1h
2h
3h
4h
5h
6h
7h
. . . . . .
Dh
Eh
0
1
2
3
4
5
6
7
i
j
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
b
c
k
d
l
BIT
e
m
n
f
g
o
h
p
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG13
SEG14
Display data is written to DDRAM every 8-bit data.
No need to wait for ACK bit to complete data transfer.
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