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BS616LV4025BC PDF预览

BS616LV4025BC

更新时间: 2024-02-03 18:23:26
品牌 Logo 应用领域
BSI 静态存储器
页数 文件大小 规格书
11页 191K
描述
Very Low Power/Voltage CMOS SRAM 256K x 16 or 512K x 8 bit switchable

BS616LV4025BC 数据手册

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Very Low Power/Voltage CMOS SRAM  
256K x 16 or 512K x 8 bit switchable  
BSI  
BS616LV4025  
„ DESCRIPTION  
„ FEATURES  
The BS616LV4025 is a high performance, very low power CMOS Static  
Random Access Memory organized as 262,144 words by 16 bits or  
524,288 bytes by 8 bits selectable by CIO pin and operates from a wide  
range of 4.5V to 5.5V supply voltage.  
• Operation voltage : 4.5~5.5V  
• Low power consumption :  
Vcc = 5.0V C-grade: 45mA (Max.) operating current  
I-grade : 50mA (Max.) operating current  
1.5uA (Typ.) CMOS standby current  
• High speed access time :  
Advanced CMOS technology and circuit techniques provide both high  
speed and low power features with a typical CMOS standby current  
of 1.5uA and maximum access time of 70/55ns in 5V operation.  
Easy memory expansion is provided by an active HIGH chip  
enable2(CE2), and active LOW chip enable1(CE1), an active LOW  
output enable(OE) and three-state output drivers.  
-70  
-55  
70ns (Max.) at Vcc=5V  
55ns (Max.) at Vcc=5V  
• Automatic power down when chip is deselected  
• Three state outputs and TTL compatible  
• Fully static operation  
The BS616LV4025 has an automatic power down feature, reducing the  
power consumption significantly when chip is deselected.  
• Data retention supply voltage as low as 1.5V  
• Easy expansion with CE1, CE2 and OE options  
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin  
The BS616LV4025 is available in DICE form and 48-pin BGA type.  
„ PRODUCT FAMILY  
POWER DISSIPATION  
SPEED  
STANDBY  
Operating  
OPERATING  
(ns)  
PRODUCT FAMILY  
Vcc RANGE  
PKG TYPE  
(ICCSB1, Max)  
(ICC, Max)  
TEMPERATURE  
Vcc = 5.0V  
Vcc = 5.0V  
15uA  
Vcc = 5.0V  
45mA  
BS616LV4025DC  
BS616LV4025BC  
BS616LV4025DI  
BS616LV4025BI  
DICE  
+0 O C to +70O  
-40 O C to +85O  
C
C
4.5 ~ 5.5V  
4.5 ~ 5.5V  
70 / 55  
70 / 55  
BGA-48-0810  
DICE  
50uA  
50mA  
BGA-48-0810  
„ BLOCK DIAGRAM  
„ PIN CONFIGURATION  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
Address  
Input  
22  
2048  
Row  
Memory Array  
2048 x 2048  
Buffer  
A8  
Decoder  
A17  
A7  
A6  
2048  
Data  
16(8)  
16(8)  
Column I/O  
Input  
D0  
Buffer  
.
.
.
.
.
.
.
.
Write Driver  
Sense Amp  
16(8)  
16(8)  
128(256)  
Data  
Output  
Buffer  
Column Decoder  
D15  
CE1  
CE2  
14(16)  
WE  
OE  
UB  
Control  
Address Input Buffer  
LB  
CIO  
A16 A0 A1 A2 A3  
A4 A5  
(SAE)  
Vdd  
Vss  
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.  
Revision 2.4  
April 2002  
R0201-BS616LV4025  
1

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