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BS616LV1013AI PDF预览

BS616LV1013AI

更新时间: 2022-12-11 23:02:14
品牌 Logo 应用领域
BSI 静态存储器
页数 文件大小 规格书
9页 259K
描述
Very Low Power/Voltage CMOS SRAM 64K X 16 bit

BS616LV1013AI 数据手册

 浏览型号BS616LV1013AI的Datasheet PDF文件第3页浏览型号BS616LV1013AI的Datasheet PDF文件第4页浏览型号BS616LV1013AI的Datasheet PDF文件第5页浏览型号BS616LV1013AI的Datasheet PDF文件第6页浏览型号BS616LV1013AI的Datasheet PDF文件第8页浏览型号BS616LV1013AI的Datasheet PDF文件第9页 
BSI  
BS616LV1013  
(1,6)  
WRITE CYCLE2  
t
WC  
ADDRESS  
(11)  
t
CW  
(5)  
CE  
t
BW  
LB,UB  
t
WR  
t
AW  
(3)  
t
WP  
(2)  
WE  
t
AS  
(4,10)  
t
t
OW  
(7)  
(8)  
t
WHZ  
D OUT  
t
DW  
(8,9)  
DH  
D IN  
NOTES:  
1. WE must be high during address transitions.  
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals  
must be active to initiate a write and any one signal can terminate a write by going inactive.  
The data input setup and hold timing should be referenced to the second transition edge of  
the signal that terminates the write.  
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.  
4. During this period, DQ pins are in the output state so that the input signals of opposite phase  
to the outputs must not be applied.  
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE  
transition, output remain in a high impedance state.  
6. OE is continuously low (OE = VIL ).  
7. DOUT is the same phase of write data of this write cycle.  
8. DOUT is the read data of next address.  
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of  
opposite phase to the outputs must not be applied to them.  
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.  
±
The parameter is guaranteed but not 100% tested.  
11. TCW is measured from the later of CE going low to the end of write.  
12. The change of Read/Write cycle must accompany with CE or address toggled.  
Revision 1.1  
R0201-BS616LV1013  
7
Jan.  
2004  

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