Very Low Power/Voltage CMOS SRAM
64K X 16 bit
BSI
BS616LV1015
DESCRIPTION
FEATURES
The BS616LV1015 is a high performance, very low power CMOS Static
Random Access Memory organized as 65,536 words by 16 bits and
operates from a wide range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.4uA and maximum access time of 55ns in 5V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
The BS616LV1015 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1015 is available in the JEDEC standard 44-pin TSOP
Type II and 48-pin BGA package.
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V
C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
• High speed access time :
-55
55ns (Max.) at Vcc = 5.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
STANDBY
Operating
(ICC, Max)
PKG TYPE
(ICCSB1, Max)
Vcc=5.0V
Vcc=5.0V
Vcc=5.0V
BS616LV1015EC
TSOP2-44
+0 O C to +70O
-40 O C to +85O
C
C
4.5V ~ 5.5V
4.5V ~ 5.5V
55
10uA
35mA
BS616LV1015AC
BS616LV1015EI
BS616LV1015AI
BGA-48-0608
TSOP2-44
55
20uA
40mA
BGA-48-0608
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
A5
A6
A7
OE
UB
LB
A8
A13
DQ15
Address
A15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
18
512
A14
A12
A7
BS616LV1015EC
BS616LV1015EI
Input
Row
Decoder
Memory Array
512 x 2048
Buffer
A6
A5
A4
17
18
19
20
21
22
WE
A15
A14
A13
A12
NC
A8
A9
A10
A11
2048
Data
Input
Buffer
16
16
16
Column I/O
DQ0
NC
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
1
2
3
4
5
6
128
Data
Output
16
A
B
C
D
E
F
LB
OE
UB
A0
A3
A1
A4
A2
NC
IO0
IO2
Buffer
Column Decoder
DQ15
IO8
CE
14
CE
WE
OE
UB
IO9
IO10
IO11
IO12
IO13
NC
A5
A6
IO1
IO3
IO4
IO5
WE
A11
Control
Address Input Buffer
VSS
VCC
IO14
IO15
NC
NC
NC
A14
A12
A9
A7
VCC
VSS
IO6
IO7
NC
LB
A11 A9 A3 A2 A1
A0 A10
NC
A15
A13
A10
Vcc
Gnd
G
H
A8
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 1.1
R0201-BS616LV1015
1
Jan.
2004
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