5秒后页面跳转
BR573D PDF预览

BR573D

更新时间: 2024-02-16 05:01:58
品牌 Logo 应用领域
飞思卡尔 - FREESCALE /
页数 文件大小 规格书
441页 2488K
描述
Integrated Processor with DMA User’s Manual

BR573D 数据手册

 浏览型号BR573D的Datasheet PDF文件第3页浏览型号BR573D的Datasheet PDF文件第4页浏览型号BR573D的Datasheet PDF文件第5页浏览型号BR573D的Datasheet PDF文件第7页浏览型号BR573D的Datasheet PDF文件第8页浏览型号BR573D的Datasheet PDF文件第9页 
11/2/95  
SECTION 1: OVERVIEW  
UM Rev 1  
Freescale Semiconductor, Inc.  
TABLE OF CONTENTS (Continued)  
Paragraph  
Number  
Page  
Number  
Title  
2.15  
Test Signals.......................................................................................................2-13  
Test Clock (TCK)...........................................................................................2-13  
Test Mode Select (TMS)..............................................................................2-13  
Test Data In (TDI)..........................................................................................2-13  
Test Data Out (TDO).....................................................................................2-13  
2.15.1  
2.15.2  
2.15.3  
2.15.4  
2.16  
Synthesizer Power (V )..........................................................................2-13  
CCSYN  
2.17  
System Power and Ground (V and GND)................................................2-13  
CC  
2.18  
Signal Summary...............................................................................................2-13  
Section 3  
Bus Operation  
3.1  
Bus Transfer Signals........................................................................................3-1  
Bus Control Signals.....................................................................................3-2  
Function Code Signals................................................................................3-3  
Address Bus (A31–A0)................................................................................3-4  
Address Strobe (AS)....................................................................................3-4  
Data Bus (D15–D0)......................................................................................3-4  
Data Strobe (DS)...........................................................................................3-4  
Bus Cycle Termination Signals..................................................................3-4  
Data Transfer and Size Acknowledge Signals  
3.1.1  
3.1.2  
3.1.3  
3.1.4  
3.1.5  
3.1.6  
3.1.7  
3.1.7.1  
(DSACK1 and DSACK0).....................................................................3-4  
Bus Error (BERR).......................................................................................3-5  
Autovector (AVEC)....................................................................................3-5  
Data Transfer Mechanism...............................................................................3-5  
Dynamic Bus Sizing.....................................................................................3-5  
Misaligned Operands...................................................................................3-7  
Operand Transfer Cases.............................................................................3-7  
Byte Operand to 8-Bit Port, Odd or Even (A0 = X)..............................3-7  
Byte Operand to 16-Bit Port, Even (A0 = 0)..........................................3-8  
Byte Operand to 16-Bit Port, Odd (A0 = 1)...........................................3-9  
Word Operand to 8-Bit Port, Aligned.....................................................3-9  
Word Operand to 16-Bit Port, Aligned...................................................3-10  
Long-word Operand to 8-Bit Port, Aligned...........................................3-10  
Long-Word Operand to 16-Bit Port, Aligned........................................3-12  
Bus Operation................................................................................................3-14  
Synchronous Operation with DSACK.....................................................3-14  
Fast Termination Cycles..............................................................................3-15  
Data Transfer Cycles........................................................................................3-16  
Read Cycle.....................................................................................................3-16  
Write Cycle.....................................................................................................3-18  
Read-Modify-Write Cycle.............................................................................3-19  
3.1.7.2  
3.1.7.3  
3.2  
3.2.1  
3.2.2  
3.2.3  
3.2.3.1  
3.2.3.2  
3.2.3.3  
3.2.3.4  
3.2.3.5  
3.2.3.6  
3.2.3.7  
3.2.4  
3.2.5  
3.2.6  
3.3  
3.3.1  
3.3.2  
3.3.3  
MOTOROLA  
MC68340 USER'S MANUAL  
v
For More Information On This Product,  
Go to: www.freescale.com  

与BR573D相关器件

型号 品牌 获取价格 描述 数据表
BR5763X ETC

获取价格

Optoelectronic
BR5767X ETC

获取价格

Optoelectronic
BR5785X ETC

获取价格

Optoelectronic
BR5817 APITECH

获取价格

Wide Band Medium Power Amplifier, 10MHz Min, 1500MHz Max, H2, TO-8B
BR5834 APITECH

获取价格

Narrow Band Medium Power Amplifier, 10MHz Min, 100MHz Max, H2, TO-8B
BR5853 APITECH

获取价格

RF AMPLIFIER MODEL
BR587-10 EDAL

获取价格

Sub-Miniature High Voltage Rectifiers
BR587-100 EDAL

获取价格

Sub-Miniature High Voltage Rectifiers
BR587-110 EDAL

获取价格

Sub-Miniature High Voltage Rectifiers
BR587-120 EDAL

获取价格

Sub-Miniature High Voltage Rectifiers