Datasheet > BD3491FS-E2

BD3491FS-E2

更新时间： 2024-01-01 14:28:52

品牌	Logo	应用领域
罗姆 - ROHM		/
页数	文件大小	规格书
34页	1235K
描述
Sound Processor with Built-in Surround Sound Function

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BD3491FS-E2 数据手册

Datasheet

BD3491FS

CONTROL SIGNAL SPECIFICATION

(1)Electrical specifications and timing for bus lines and I/O stages

SDA

^tBUF

^tHD;STA

^tF

^tSP

^tR

^tLOW

SCL

^tSU;STO

^tHD;STA

^tSU;DAT ^tSU;STA

^tHD;DAT

^tHIGH

Figure 12. Definition of timing on the I²C-BUS

Table 1. Characteristics of the SDA and SCL bus lines for I²C-BUS devices

Parameter

Fast-mode

Min. Max.

400

Symbol

Unit

kHz

SCL clock frequency

fSCL

tBUF

Bus free time between a STOP and START condition

Hold time (repeated) START condition. After this period, the first clock

pulse is generated

1.3

－

µs

tHD;STA

0.6

－

µs

LOW period of the SCL clock

tLOW

1.3

0.6

－

µs

HIGH period of the SCL clock

Set-up time for a repeated START condition

Data hold time

tHIGH

tSU;STA

tHD;DAT

tSU;DAT

tSU;STO

0.6

300*

0.6

Data set-up time

Set-up time for STOP condition

All values referred to VIH min and VIL max levels (see Table 2).

*About 7(tHD;DAT), 8(tSU;DAT), make it the setup which a margin is fully in .

Table 2. Characteristics of the SDA and SCL I/O stages for I²C-BUS devices

Parameter

Fast-mode

Symbol

Unit

Min.

-0.3

2.3

Max.

LOW level input voltage:

VIL

VIH

tSP

11 HIGH level input voltage:

12 Pulse width of spikes which must be suppressed by the input filter.

LOW level output voltage (open drain or open collector): at 3mA sink

current.

VOL1

0.4

Input current in each I/O pin with an input voltage between 0.4V and

4.5V.

-10

µA

SCL clock frequency:250kHz

Figure 13. A command timing example in the I²C data transmission.

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