List of Figures
Figure 3.1
BlueCore4-External 8 x 8mm Device Pinout (BC417143B-IQN-E4)........................................... 10
BlueCore4-External 6 x 6mm Device Pinout (BC417143B-IRN-E4)........................................... 16
BlueCore4-External Device Diagram.......................................................................................... 47
BlueCore HCI Stack.................................................................................................................... 50
BlueCore RFCOMM Stack.......................................................................................................... 53
Virtual Machine ........................................................................................................................... 55
HID Stack.................................................................................................................................... 56
Basic Rate and Enhanced Data Rate Packet Structure.............................................................. 58
π/4 DQPSK Constellation Pattern............................................................................................... 59
8DPSK Constellation Pattern...................................................................................................... 60
Circuit TX/RF_A and TX/RF_B ................................................................................................... 61
Circuit RX_IN .............................................................................................................................. 62
TCXO Clock Accuracy ................................................................................................................ 64
Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting.................................. 65
Crystal Driver Circuit................................................................................................................... 67
Crystal Equivalent Circuit............................................................................................................ 67
Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency...................... 71
Crystal Driver Transconductance vs. Driver Level Register Setting ........................................... 72
Crystal Driver Negative Resistance as a Function of Drive Level Setting .................................. 73
Memory Write Cycle.................................................................................................................... 76
Memory Read Cycle ................................................................................................................... 77
Universal Asynchronous Receiver.............................................................................................. 78
Break Signal................................................................................................................................ 79
UART Bypass Architecture ......................................................................................................... 80
USB Connections for Self-Powered Mode.................................................................................. 82
USB Connections for Bus-Powered Mode.................................................................................. 83
USB_DETACH and USB_WAKE_UP Signal.............................................................................. 84
Write Operation........................................................................................................................... 87
Read Operation........................................................................................................................... 87
BlueCore4-External as PCM Interface Master............................................................................ 89
BlueCore4-External as PCM Interface Slave.............................................................................. 89
Long Frame Sync (Shown with 8-bit Companded Sample)........................................................ 90
Short Frame Sync (Shown with 16-bit Sample).......................................................................... 90
Multi-slot Operation with Two Slots and 8-bit Companded Samples.......................................... 91
GCI Interface............................................................................................................................... 91
16-Bit Slot Length and Sample Formats..................................................................................... 92
PCM Master Timing Long Frame Sync....................................................................................... 94
PCM Master Timing Short Frame Sync ...................................................................................... 94
PCM Slave Timing Long Frame Sync......................................................................................... 96
PCM Slave Timing Short Frame Sync ........................................................................................ 96
Example EEPROM Connection ................................................................................................ 101
Example TXCO Enable OR Function........................................................................................ 102
Application Circuit for Radio Characteristics Specification ....................................................... 106
BlueCore4-External 96-Ball TFBGA Package Dimensions....................................................... 107
BlueCore4-External 96-Ball VFBGA Package Dimensions ...................................................... 108
Figure 3.2
Figure 7.1
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 10.1
Figure 10.2
Figure 10.3
Figure 11.1
Figure 11.2
Figure 11.3
Figure 11.4
Figure 11.5
Figure 11.6
Figure 11.7
Figure 11.8
Figure 11.9
Figure 11.10
Figure 11.11
Figure 11.12
Figure 11.13
Figure 11.14
Figure 11.15
Figure 11.16
Figure 11.17
Figure 11.18
Figure 11.19
Figure 11.20
Figure 11.21
Figure 11.22
Figure 11.23
Figure 11.24
Figure 11.25
Figure 11.26
Figure 11.27
Figure 11.28
Figure 11.29
Figure 11.30
Figure 11.31
Figure 11.32
Figure 12.1
Figure 13.1
Figure 13.2
List of Tables
Table 10.1
Data Rate Schemes.................................................................................................................... 58
Production Information
© Cambridge Silicon Radio Limited 2005
BC417143B-ds-001Pg
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