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BA3257FPHFP

更新时间： 2024-02-13 10:39:51
品牌 Logo 应用领域
罗姆 - ROHM 稳压器电容器陶瓷电容器
页数 文件大小 规格书
14页 101K
描述
Dual Low Drop Out Regulator Ceramic Capacitor Available

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中文翻译

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BA3257FPHFP 数据手册

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0
R
XCR3512XL: 512 Macrocell CPLD  
0
14  
DS081 (v1.2) September 4, 2001  
Advance Product Specification  
Features  
Description  
•
•
•
•
•
Lowest power 512 macrocell CPLD  
The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at  
power sensitive designs that require leading edge program-  
mable logic solutions. A total of 32 function blocks provide  
12,800 usable gates. Pin-to-pin propagation delays are  
7.5 ns with a maximum system frequency of 127 MHz.  
7.5 ns pin-to-pin logic delays  
System frequencies up to 127 MHz  
512 macrocells with 12,800 usable gates  
Available in small footprint packages  
-
-
-
208-pin PQFP (180 user I/O)  
256-ball FBGA (212 user I/O)  
324-ball FBGA (260 user I/O)  
TotalCMOS™ Design Technique for  
Fast Zero Power  
Xilinx offers a TotalCMOS CPLD, both in process technol-  
ogy and design technique. Xilinx employs a cascade of  
CMOS gates to implement its sum of products instead of  
the traditional sense amp approach. This CMOS gate imple-  
mentation allows Xilinx to offer CPLDs that are both high  
performance and low power, breaking the paradigm that to  
have low power, you must have low performance. Refer to  
•
•
Optimized for 3.3V systems  
-
-
-
Ultra low power operation  
5V tolerant I/O pins with 3.3V core supply  
Advanced 0.35 micron five layer metal EEPROM  
process  
FZP™ CMOS design technology  
-
Advanced system features  
Figure 1 and Table 1 showing the I  
vs. Frequency of our  
CC  
-
-
-
-
-
-
-
-
In-system programming  
Input registers  
Predictable timing model  
Up to 23 clocks available per function block  
Excellent pin retention during design changes  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Four global clocks  
XCR3512XL TotalCMOS CPLD (data taken with 32  
up/down, loadable 16-bit counters at 3.3V, 25°C).  
140  
120  
100  
80  
Eight product term control terms per function block  
•
•
•
Fast ISP programming times  
Port Enable pin for additional I/O  
2.7V to 3.6V supply voltage at industrial grade voltage  
range  
60  
•
•
•
Programmable slew rate control per output  
Security bit prevents unauthorized access  
40  
20  
Refer to XPLA3 family data sheet (DS012) for  
architecture description  
0
0
20  
40  
60  
80  
100 120 140 160  
Frequency (MHz)  
DS024_01_112700  
Figure 1: XCR3512XL Typical I vs. Frequency at V  
CC  
CC  
= 3.3V, 25°C  
Table 1: Typical I vs. Frequency at V = 3.3V, 25°C  
CC  
CC  
Frequency (MHz)  
Typical I (mA)  
0
1
10  
TBD  
20  
40  
60  
80  
100  
120  
140  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
CC  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS081 (v1.2) September 4, 2001  
www.xilinx.com  
1
Advance Product Specification  
1-800-255-7778  
 
 
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