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ATF22LV10CQZ-30SC PDF预览

ATF22LV10CQZ-30SC

更新时间: 2024-02-17 09:32:45
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
19页 347K
描述
Highperformance EE PLD

ATF22LV10CQZ-30SC 数据手册

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Features  
3.0V to 5.5V Operating Range  
Lowest Power in It Class  
Advanced Low-voltage, Zero-power, Electrically Erasable Programmable Logic Device  
“Zero” Standby Power (25 µA Maximum) (Input Transition Detection)  
Low-voltage Equivalent of ATF22V10CZ  
Ideal for Battery Powered Systems  
CMOS- and TTL-compatible Inputs and Outputs  
Inputs are 5V Tolerant  
High-  
Latch Feature Hold Inputs to Previous Logic States  
EE Technology  
performance  
EE PLD  
– Reprogrammable  
– 100% Tested  
High-reliability CMOS Process  
– 20-year Data Retention  
– 10,000 Erase/Write Cycles  
ATF22LV10CZ  
– 2,000V ESD Protection  
– 200 mA Latch-up Immunity  
ATF22LV10CQZ  
Commercial and Industrial Temperature Ranges  
Dual Inline and Surface Mount Standard Pinouts  
Green Package Options (Pb/Halide-free/RoHS Compliant) Available  
1. Description  
The ATF22LV10CZ/CQZ is a high-performance CMOS (electrically erasable) pro-  
grammable logic device (PLD) that utilizes Atmel’s proven electrically erasable Flash  
memory technology and provides 25 ns speed with standby current of 25 µA maxi-  
mum. All speed ranges are specified over the 3.0V to 5.5V range for industrial and  
commercial temperature ranges.  
The ATF22LV10CZ/CQZ provides a low-voltage and edge-sensing “zero” power  
CMOS PLD solution with “zero” standby power (5 µA typical). The  
ATF22LV10CZ/CQZ powers down automatically to the zero power mode through  
Atmel’s patented Input Transition Detection (ITD) circuitry when the device is idle. The  
ATF22LV10CZ/CQZ is capable of operating at supply voltages down to 3.0V. Pin  
“keeper” circuits on input and output pins hold pins to their previous logic levels when  
idle, which eliminate static power consumed by pull-up resistors. The “CQZ” combines  
this low high-frequency ICC of the “Q” design with the “Z” feature.  
The ATF22LV10CZ/CQZ macrocell incorporates a variable product term architecture.  
Each output is allocated from 8 to 16 product terms which allows highly complex logic  
functions to be realized. Two additional product terms are included to provide syn-  
chronous reset and asynchronous reset. These additional product terms are common  
to all 10 registers and are automatically cleared upon power-up. Register Preload sim-  
plifies testing. A security fuse prevents unauthorized copying of programmed fuse  
patterns.  
0779L–PLD–12/05  

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