POSEICO SPA
Via N. Lorenzi 8, 16152 Genova - ITALY
Tel. +39 010 6556234 - Fax +39 010 6557519
Sales Office:
POSEICO
POSEICO SPA
POwer SEmiconductors Italian COrporation
Tel. +39 010 6556775 - Fax +39 010 6445141
FAST SWITCHING THYRISTOR
ATF827
Repetitive voltage up to
Mean on-state current
Surge current
1400 V
900 A
10 kA
25 µs
FINAL SPECIFICATION
Turn-off time
mag 06 - ISSUE : 05
Tj
Symbol
Characteristic
Conditions
Value
Unit
[°C]
BLOCKING
V RRM
V RSM
V DRM
I RRM
I DRM
Repetitive peak reverse voltage
Non-repetitive peak reverse voltage
Repetitive peak off-state voltage
Repetitive peak reverse current
Repetitive peak off-state current
125
125
125
125
125
1400
1500
1400
75
V
V
V
V=VRRM
V=VDRM
mA
mA
75
CONDUCTING
I T (AV)
I T (AV)
I TSM
I² t
Mean on-state current
Mean on-state current
Surge on-state current, non repetitive
I² t
180°sin, 50 Hz, Th=55°C, double side cooled
180°sin, 1 kHz, Th=55°C, double side cooled
sine wave, 10 ms
900
835
A
A
125
10
kA
without reverse voltage
500 x1E3
2
A²s
V
V T
On-state voltage
On-state current =
1600 A
25
V T(TO)
r T
Threshold voltage
125
1,32
V
On-state slope resistance
125 0,350
mohm
SWITCHING
di/dt
dv/dt
td
Critical rate of rise of on-state current, min
Critical rate of rise of off-state voltage, min
Gate controlled delay time, typical
From 75% VDRM up to 1200 A, gate 20V 10 ohm
Linear ramp up to 70% of VDRM
125
125
25
400
600
0,6
25
A/µs
V/µs
µs
VD=100V, gate source 20V, 10 ohm , tr=1 µs
tq
Circuit commutated turn-off time
di/dt = 20
dV/dt = 200 V/µs , up to 75% VDRM
di/dt = 60 A/µs, I I = 1000
VR = 50
A/µs, I I = 400
A
125
µs
Q rr
I rr
I H
Reverse recovery charge
Peak reverse recovery current
Holding current, typical
A
125
330
168
45
µC
A
V
VD=5V, gate open circuit
VD=5V, tp=30µs
25
25
mA
mA
I L
Latching current, typical
70
GATE
V GT
I GT
Gate trigger voltage
VD=5V
25
25
125
25
25
25
25
25
3,5
350
0,25
30
V
mA
V
Gate trigger current
VD=5V
V GD
V FGM
Non-trigger gate voltage, min.
Peak gate voltage (forward)
Peak gate current
VD=VDRM
V
I
FGM
10
A
V RGM
P GM
Peak gate voltage (reverse)
Peak gate power dissipation
Average gate power dissipation
5
V
Pulse width 100 µs
150
3
W
W
P G(AV)
MOUNTING
R th(j-h)
T j
Thermal impedance, DC
Operating junction temperature
Mounting force
Junction to heatsink, double side cooled
37
°C/kW
°C
-30 / 125
11.0 / 13.0
320
F
kN
Mass
g
tq code
D 10 µs C 12 µs B 15 µs A 20 µs L 25 µs
M 30 µs N 35 µs P 40 µs R 45 µs S 50 µs
T 60 µs U 70 µs W 80 µs X 100µs Y 150µs
tq code
ORDERING INFORMATION : ATF827 S 14 L
VDRM&VRRM/100
standard specification
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