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ATF22V10C-10SU-T

更新时间： 2024-01-31 02:51:08
品牌 Logo 应用领域
美国微芯 - MICROCHIP 时钟输入元件光电二极管可编程逻辑
页数 文件大小 规格书
22页 1911K
描述
Flash PLD, 10ns, CMOS, PDSO24

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ATF22V10C-10SU-T 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：SOP,Reach Compliance Code：compliant
风险等级：5.61最大时钟频率：90 MHz
JESD-30 代码：R-PDSO-G24长度：15.4 mm
专用输入次数：10I/O 线路数量：10
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C组织：10 DEDICATED INPUTS, 10 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
可编程逻辑类型：FLASH PLD传播延迟：10 ns
座面最大高度：2.65 mm最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.5 mm
Base Number Matches：1

ATF22V10C-10SU-T 数据手册

 浏览型号ATF22V10C-10SU-T的Datasheet PDF文件第4页浏览型号ATF22V10C-10SU-T的Datasheet PDF文件第5页浏览型号ATF22V10C-10SU-T的Datasheet PDF文件第6页浏览型号ATF22V10C-10SU-T的Datasheet PDF文件第8页浏览型号ATF22V10C-10SU-T的Datasheet PDF文件第9页浏览型号ATF22V10C-10SU-T的Datasheet PDF文件第10页 
Atmel ATF22V10C(Q)  
4.7  
Power-up Reset  
The registers in the Atmel® ATF22V10Cs are designed to reset during power-up. At a point delayed slightly from  
CC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the  
V
output buffer.  
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the  
uncertainty of how VCC actually rises in the system, the following conditions are required:  
1. The VCC rise must be monotonic, and starts below 0.7V  
2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high  
3. The clock must remain stable during tPR  
Figure 4-1. Power-up Reset Timing  
V
R
ST  
POWER  
t
PR  
REGISTERED  
OUTPUTS  
t
S
t
W
CLOCK  
4.8  
Preload of Registered Outputs  
The ATF22V10C registers are provided with circuitry to allow loading of each register with either a high or a low.  
This feature will simplify testing since any state can be forced into the registers to control test sequencing. A  
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC  
file preload sequence will be done automatically by most of the approved programmers after the programming.  
5.  
6.  
Electronic Signature Word  
There are 64-bits of programmable memory that are always available to the user, even if the device is secured.  
These bits can be used for user-specific data.  
Security Fuse Usage  
A single fuse is provided to prevent unauthorized copying of the ATF22V10C fuse patterns. Once programmed,  
fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.  
The security fuse should be programmed last, as its effect is immediate.  
7.  
Programming/Erasing  
Programming/erasing is performed using standard PLD programmers. See “CMOS PLD Programming Hardware  
and Software Support” for information on software/programming.  
Table 7-1.  
Programming/Erasing  
Parameter  
tPR  
Description  
Typ  
600  
3.8  
Max  
1,000  
4.5  
Units  
ns  
Power-up Reset Time  
Power-up Reset Voltage  
VRST  
V
7
0735U–PLD–7/10  
1...45678910...22

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