Datasheet > 可编程逻辑 > 可编程逻辑器件> ATF22V10C-10PC

ATF22V10C-10PC

更新时间： 2024-02-27 16:51:33

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程逻辑器件
页数	文件大小	规格书
8页	237K
描述
High Performance E2 PLD

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数据手册

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ATF22V10C-10PC 数据手册

ATF22V10C

Power Down AC Characteristics ^{(1, 2, 3)}

-5

-7

-10

Symbol Parameter

Min

Max

Min

7.5

Max

Min

Max

Units

Valid Input Before PD High

Valid OE Before PD High

Valid Clock Before PD High

Input Don’t Care After PD High

OE Don’t Care After PD High

Clock Don’t Care After PD High

PD Low to Valid Input

IVDH

GVDH

CVDH

DHIX

DHGX

DHCX

DLIV

7.5

PD Low to Valid OE

DLGV

DLCV

DLOV

PD Low to Valid Clock

PD Low to Valid Output

3. Clock and input transitions are ignored.

Notes: 1. Output data is latched and held.

2. HI-Z outputs remain HI-Z.

Output Test Loads:

Input Test Waveforms and

Measurement Levels

Commercial

t_R, t_F< 3 ns

Pin Capacitance (f = 1 MHz, T = 25°C) ⁽¹⁾

Typ

Max

Units

Conditions

= 0V

OUT

Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

Power Up Reset

The registers in the ATF22V10Cs are designed to reset

1. The V rise must be monotonic, and starts below

during power up. At a point delayed slightly from V

0.7V,

crossing V

, all registers will be reset to the low state.

RST

2. After reset occurs, all input and feedback setup times

must be met before driving the clock pin high, and

The output state will depend on the polarity of the output

buffer.

3. The clock must remain stable during t

This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the un-

certainty of how V actually rises in the system, the fol-

lowing conditions are required:

1 2 3 456 7 8

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