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ATF22LV10C-15JL PDF预览

ATF22LV10C-15JL

更新时间: 2022-12-01 19:59:10
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
19页 1813K
描述
Flash PLD, 15ns, CMOS, PQCC28, PLASTIC, MS-018AB, LCC-28

ATF22LV10C-15JL 数据手册

 浏览型号ATF22LV10C-15JL的Datasheet PDF文件第4页浏览型号ATF22LV10C-15JL的Datasheet PDF文件第5页浏览型号ATF22LV10C-15JL的Datasheet PDF文件第6页浏览型号ATF22LV10C-15JL的Datasheet PDF文件第8页浏览型号ATF22LV10C-15JL的Datasheet PDF文件第9页浏览型号ATF22LV10C-15JL的Datasheet PDF文件第10页 
Atmel ATF22LV10C  
8.  
Power-down Mode  
The Atmel® ATF22LV10C includes an optional pin controlled power-down feature. When this mode is enabled, the  
PD pin acts as the power-down pin (Pin 4 on the DIP/SOIC packages and Pin 5 on the PLCC package). When the  
PD pin is high, the device supply current is reduced to less than 100mA. During power-down, all output data and  
internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any  
outputs which were in an undetermined state at the onset of power-down will remain at the same state. During  
power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to  
insure that pins do not float to indeterminate levels, further reducing system power. The power-down pin feature is  
enabled in the logic design file. Designs using the power-down pin may not use the PD pin logic array input.  
However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback  
product term array inputs.  
PD pin configuration is controlled by the design file, and appears as a separate fuse bit in the JEDEC file. When  
the power-down feature is not specified in the design file, the IN/PD pin will be configured as a regular logic input.  
Note:  
Some programmers list the 22V10 JEDEC-compatible 22V10C (no PD used) separately from the non-22V10 JEDEC-  
compatible 22V10CEX (with PD used).  
Figure 8-1. Input Diagram  
VCC  
100K  
INPUT  
ESD  
PROTECTION  
CIRCUIT  
Figure 8-2. I/O Diagram  
V
CC  
OE  
DATA  
I/O  
V
CC  
100K  
INPUT  
7
0780M–PLD–7/10  

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