Datasheet > ATF22LV10C-15JL

ATF22LV10C-15JL

更新时间： 2022-12-01 19:59:10

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
19页	1813K
描述
Flash PLD, 15ns, CMOS, PQCC28, PLASTIC, MS-018AB, LCC-28

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ATF22LV10C-15JL 数据手册

3.7

Power-up Reset

The registers in the Atmel^®ATF22LV10C are designed to reset during power-up. At a point delayed slightly from

_CCcrossing V_RST, all registers will be reset to the low state. The output state will depend on the polarity of the

buffer.

This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the

uncertainty of how V_CCactually rises in the system, the following conditions are required:

1. The V_CCrise must be monotonic and start below 0.7V

2. The clock must remain stable during T_PR

3. After T_PR, all input and feedback setup times must be met before driving the clock pin high

3.8

Preload of Register Outputs

The ATF22LV10C registers are provided with circuitry to allow loading of each register with either a high or a low.

This feature will simplify testing since any state can be forced into the registers to control test sequencing. A

JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC

file preload sequence will be done automatically by most of the approved programmers after the programming.

Electronic Signature Word

There are 64-bits of programmable memory that are always available to the user, even if the device is secured.

These bits can be used for user-specific data.

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF22LV10C fuse patterns. Once programmed,

fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.

The security fuse should be programmed last, as its effect is immediate.

Programming/Erasing

Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware &

Software Support for information on software/programming.

Table 6-1.

Programming/Erasing

Parameter

T_PR

Description

Typ

600

2.5

Max

1,000

3.0

Units

Power-up Reset Time

Power-up Reset Voltage

V_RST

Input and I/O Pin-keeper

All ATF22V10C family members have internal input and I/O pin-keeper circuits. Therefore, whenever inputs or

I/Os are not being driven externally, they will maintain their last driven state. This ensures that all logic array inputs

and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by

TTL-compatible drivers (see Input and I/O diagrams on page 7).

Atmel ATF22LV10C

0780M–PLD–7/10

1...3 4 567 8 9...19

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