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ATF20V8BQL-15JC PDF预览

ATF20V8BQL-15JC

更新时间: 2024-02-26 22:19:32
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
17页 761K
描述
High- Performance EE PLD

ATF20V8BQL-15JC 数据手册

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Input and I/O Pull-Ups  
All ATF20V8B family members have internal input and I/O  
pull-up resistors. Therefore, whenever inputs or I/Os are  
not being driven externally, they will float to VCC. This  
ensures that all logic array inputs are at known states.  
These are relatively weak active pull-ups that can easily be  
overdriven by TTL-compatible drivers (see input and I/O  
diagrams below).  
Input Diagram  
I/O Diagram  
Functional Logic Diagram Description  
The Logic Option and Functional Diagrams describe the  
ATF20V8B architecture. Eight configurable macrocells can  
be configured as a registered output, combinatorial I/O,  
combinatorial output, or dedicated input.  
subsets can be found in each of the configuration modes  
described in the following pages. The user can download  
the listed subset device JEDEC programming file to the  
PLD programmer, and the ATF20V8B can be configured to  
act like the chosen device. Check with your programmer  
manufacturer for this capability.  
The ATF20V8B can be configured in one of three different  
modes. Each mode makes the ATF20V8B look like a dif-  
ferent device. Most PLD compilers can choose the right  
mode automatically. The user can also force the selection  
by supplying the compiler with a mode selection. The deter-  
mining factors would be the usage of register versus com-  
binatorial outputs and dedicated outputs versus outputs  
with output enable control.  
Unused product terms are automatically disabled by the  
compiler to decrease power consumption. A Security  
Fuse, when programmed, protects the content of the  
ATF20V8B. Eight bytes (64 fuses) of User Signature are  
accessible to the user for purposes such as storing project  
name, part number, revision, or date. The User Signature  
is accessible regardless of the state of the Security Fuse.  
The ATF20V8B universal architecture can be programmed  
to emulate many 24-pin PAL devices. These architectural  
ATF20V8B  
6

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