Datasheet > ATF16V8CZ-12JL

ATF16V8CZ-12JL

更新时间： 2022-12-01 20:06:20

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
26页	585K
描述
Flash PLD, 12ns, CMOS, PQCC20, PLASTIC, MS-018AA, LCC-20

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ATF16V8CZ-12JL 数据手册

ATF16V8CZ

4.5

Power-up Reset

The ATF16V8CZ’s registers are designed to reset during power-up. At a point delayed slightly

from V_CCcrossing V_RST, all registers will be reset to the low state. As a result, the registered out-

put state will always be high on power-up.

This feature is critical for state machine initialization. However, due to the asynchronous nature

of reset and the uncertainty of how V_CCactually rises in the system, the following conditions are

required:

1. The V_CCrise must be monotonic, from below 0.7V,

2. After reset occurs, all input and feedback setup times must be met before driving the

clock term high, and

3. The signals from which the clock is derived must remain stable during t_PR

Parameter

t_PR

Description

Typ

600

3.8

Max

Units

Power-up Reset Time

Power-up Reset Voltage

1,000

4.5

V_RST

4.6

Preload of Registered Outputs

The ATF16V8CZ’s registers are provided with circuitry to allow loading of each register with

either a high or a low. This feature will simplify testing since any state can be forced into the reg-

isters to control test sequencing. A JEDEC file with preload is generated when a source file with

vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automati-

cally by approved programmers.

5. Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF16V8CZ fuse patterns.

Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature

remains accessible.

The security fuse should be programmed last, as its effect is immediate.

0453H–PLD–7/05

1...4 5 678 9 10...26

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