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ATF16V8BQL-15XC PDF预览

ATF16V8BQL-15XC

更新时间: 2024-01-10 11:01:46
品牌 Logo 应用领域
爱特美尔 - ATMEL 闪存
页数 文件大小 规格书
17页 639K
描述
High- Performance Flash PLD

ATF16V8BQL-15XC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:7.62
Is Samacsys:N架构:PAL-TYPE
最大时钟频率:45 MHzJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:6.5 mm
湿度敏感等级:2专用输入次数:8
I/O 线路数量:8输入次数:18
输出次数:8产品条款数:64
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C组织:8 DEDICATED INPUTS, 8 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:5 V
可编程逻辑类型:FLASH PLD传播延迟:15 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Programmable Logic Devices最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:4.4 mmBase Number Matches:1

ATF16V8BQL-15XC 数据手册

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Electronic Signature Word  
There are 64 bits of programmable memory that are always  
available to the user, even if the device is secured. These  
bits can be used for user-specific data.  
Input and I/O Pull-Ups  
All ATF16V8B family members have internal input and I/O  
pull-up resistors. Therefore, whenever inputs or I/Os are  
not being driven externally, they will float to VCC. This  
ensures that all logic array inputs are at known states.  
These are relatively weak active pull-ups that can easily be  
overdriven by TTL-compatible drivers (see input and I/O  
diagrams below).  
Programming/Erasing  
Programming/erasing is performed using standard PLD  
programmers. See CMOS PLD Programming Hardware  
and Software Support for information on software/program-  
ming.  
Input Diagram  
I/O Diagram  
Functional Logic Diagram Description  
The Logic Option and Functional Diagrams describe the  
ATF16V8B architecture. Eight configurable macrocells can  
be configured as a registered output, combinatorial I/O,  
combinatorial output, or dedicated input.  
subsets can be found in each of the configuration modes  
described in the following pages. The user can download  
the listed subset device JEDEC programming file to the  
PLD programmer, and the ATF16V8B can be configured to  
act like the chosen device. Check with your programmer  
manufacturer for this capability.  
The ATF16V8B can be configured in one of three different  
modes. Each mode makes the ATF16V8B look like a differ-  
ent device. Most PLD compilers can choose the right  
mode automatically. The user can also force the selection  
by supplying the compiler with a mode selection. The deter-  
mining factors would be the usage of register versus com-  
binatorial outputs and dedicated outputs versus outputs  
with output enable control.  
Unused product terms are automatically disabled by the  
compiler to decrease power consumption. A Security Fuse,  
when programmed, protects the content of the ATF16V8B.  
Eight bytes (64 fuses) of User Signature are accessible to  
the user for purposes such as storing project name, part  
number, revision, or date. The User Signature is accessible  
regardless of the state of the Security Fuse.  
The ATF16V8B universal architecture can be programmed  
to emulate many 20-pin PAL devices. These architectural  
Compiler Mode Selection  
Registered  
Complex  
Simple  
Auto Select  
P16V8  
ABEL, Atmel-ABEL  
CUPL  
P16V8R  
P16V8C  
P16V8AS  
G16V8AS  
GAL16V8_C8(1)  
“Simple”  
G16V8MS  
GAL16V8_R(1)  
“Registered”  
P16V8R  
G16V8MA  
GAL16V8_C7(1)  
“Complex”  
P16V8C  
G16V8  
LOG/iC  
GAL16V8  
GAL16V8A  
P16V8A  
G16V8  
OrCAD-PLD  
PLDesigner  
Tango-PLD  
P16V8C  
G16V8R  
G16V8C  
G16V8AS  
Note:  
1. Only applicable for version 3.4 or lower.  
ATF16V8B  
6

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