Datasheet > ATF16V8C_99

ATF16V8C_99

更新时间： 2022-12-27 23:41:19

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
18页	504K
描述
Highperformance EE PLD

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数据手册

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ATF16V8C_99 数据手册

Features

• Industry-standard Architecture

– Emulates Many 20-pin PALs^®

– Low-cost Easy-to-use Software Tools

• High-speed Electrically-erasable Programmable Logic Devices

– 5 ns Maximum Pin-to-pin Delay

• Low-power - 100 µA Pin-controlled Power-down Mode Option

• CMOS and TTL Compatible Inputs and Outputs

– I/O Pin Keeper Circuits

• Advanced Flash Technology

– Reprogrammable

– 100% Tested

• High-reliability CMOS Process

– 20 Year Data Retention

High-

performance

EE PLD

– 100 Erase/Write Cycles

– 2,000V ESD Protection

– 200 mA Latchup Immunity

• Commercial and Industrial Temperature Ranges

• Dual-in-line and Surface Mount Packages in Standard Pinouts

• PCI Compliant

ATF16V8C

Block Diagram

Note:

1. Includes optional PD control pin.

TSSOP

Pin Configurations

All Pinouts Top View

I/CLK

VCC

I/O

Pin Name Function

PD/I3

I/O

CLK

Clock

I/O

Logic Inputs

Bidirectional Buffers

Output Enable

+5V Supply

Power-down

I/O

VCC

I/O

GND

I9/OE

DIP/SOIC

PLCC

I/CLK

20 VCC

19 I/O

18 I/O

17 I/O

16 I/O

15 I/O

14 I/O

13 I/O

12 I/O

11 I9/OE

PD/I3

18 I/O

17 I/O

16 I/O

15 I/O

14 I/O

PD/I3

Rev. 0425G–08/99

GND 10

12 3 4 5 6 7...18

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