Datasheet > ATF16V8B-10JJ

ATF16V8B-10JJ

更新时间： 2022-12-01 20:04:04

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
26页	625K
描述
Flash PLD, 10ns, CMOS, PQCC20, PLASTIC, MS-018AA, LCC-20

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ATF16V8B-10JJ 数据手册

ATF16V8B/BQ/BQL

4.6

Power-up Reset

The registers in the ATF16V8Bs are designed to reset during power-up. At a point delayed

slightly from V_CCcrossing V_RST, all registers will be reset to the low state. As a result, the regis-

tered output state will always be high on power-up.

This feature is critical for state machine initialization. However, due to the asynchronous nature

of reset and the uncertainty of how V_CCactually rises in the system, the following conditions are

required:

1. The V_CCrise must be monotonic,

2. After reset occurs, all input and feedback setup times must be met before driving the

clock pin high, and

3. The clock must remain stable during t_PR

Figure 4-1. Power-up Reset Waveforms

Table 4-2.

Parameter

Power-up Reset Parameters

Description

Typ

Max

Units

Power-up

Reset Time

t_PR

600

1,000

Power-up

Reset Voltage

V_RST

3.8

4.5

4.7

Preload of Registered Outputs

The ATF16V8B’s registers are provided with circuitry to allow loading of each register with either

a high or a low. This feature will simplify testing since any state can be forced into the registers

to control test sequencing. A JEDEC file with preload is generated when a source file with vec-

tors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically

by most of the approved programmers after the programming.

5. Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF16V8B fuse patterns. Once

programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains

accessible.

The security fuse should be programmed last, as its effect is immediate.

0364J–PLD–7/05

1...4 5 678 9 10...26

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