Datasheet > ATF1508ASVL-20AJ100

ATF1508ASVL-20AJ100

更新时间： 2024-02-24 06:11:20

品牌	Logo	应用领域
爱特美尔 - ATMEL		时钟输入元件可编程逻辑
页数	文件大小	规格书
28页	577K
描述
EE PLD, 20ns, PQFP100, 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-026AED, TQFP-100

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ATF1508ASVL-20AJ100 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-026AED, TQFP-100
针数：	100	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.73
最大时钟频率：	83.3 MHz	JESD-30 代码：	S-PQFP-G100
JESD-609代码：	e3	长度：	14 mm
湿度敏感等级：	3	专用输入次数：
I/O 线路数量：	80	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 80 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	可编程逻辑类型：	EE PLD
传播延迟：	20 ns	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	14 mm
Base Number Matches：	1

ATF1508ASVL-20AJ100 数据手册

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Description

The ATF1508ASV(L) is a high-performance, high-density complex programmable logic

device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 128

logic macrocells and up to 100 inputs, it easily integrates logic from several TTL, SSI,

MSI, LSI and classic PLDs. The ATF1508ASV(L)’s enhanced routing switch matrices

increase usable gate count and increase odds of successful pin-locked design

modifications.

The ATF1508ASV(L) has up to 96 bi-directional I/O pins and four dedicated input pins,

depending on the type of device package selected. Each dedicated pin can also serve

as a global control signal, register clock, register reset or output enable. Each of these

control signals can be selected for use individually within each macrocell.

Each of the 128 macrocells generates a buried feedback that goes to the global bus.

Each input and I/O pin also feeds into the global bus. The switch matrix in each logic

block then selects 40 individual signals from the global bus. Each macrocell also gener-

ates a foldback logic term that goes to a regional bus. Cascade logic between

macrocells in the ATF1508ASV(L) allows fast, efficient generation of complex logic func-

tions. The ATF1508ASV(L) contains eight such logic chains, each capable of creating

sum term logic with a fan-in of up to 40 product terms.

The ATF1508ASV(L) macrocell, shown in Figure 1, is flexible enough to support highly-

complex logic functions operating at high-speed. The macrocell consists of five sections:

product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,

output select and enable, and logic array inputs.

Unused macrocells are automatically disabled by the compiler to decrease power con-

sumption. A security fuse, when programmed, protects the contents of the

ATF1508ASV(L). Two bytes (16 bits) of User Signature are accessible to the user for

purposes such as storing project name, part number, revision or date. The User Signa-

ture is accessible regardless of the state of the security fuse.

The ATF1508ASV(L) device is an in-system programmable (ISP) device. It uses the

industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully-compliant with

JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be pro-

grammed without removing it from the printed circuit board. In addition to simplifying the

manufacturing flow, ISP also allows design modifications to be made in the field via

software.

Product Terms and Select

Mux

Each ATF1508ASV(L) macrocell has five product terms. Each product term receives as

its inputs all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as

needed to the macrocell logic gates and control signals. The PTMUX programming is

determined by the design compiler, which selects the optimum macrocell configuration.

OR/XOR/CASCADE Logic

The ATF1508ASV(L)’s logic structure is designed to efficiently support all types of logic.

Within a single macrocell, all the product terms can be routed to the OR gate, creating a

5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells,

this can be expanded to as many as 40 product terms with little additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic

functions. One input to the XOR comes from the OR sum term. The other XOR input can

be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level

input allows polarity selection. For registered functions, the fixed levels allow DeMorgan

minimization of product terms. The XOR gate is also used to emulate T- and JK-type

flip-flops.

ATF1508ASV(L)

1408H–PLD–7/05

1 2 345 6 7...28

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与ATF1508ASVL-20AJ100相关器件

型号	品牌	描述	获取价格	数据表
ATF1508ASVL-20AL100	ATMEL	EE PLD, 20ns, PQFP100, 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-026AED, TQFP-10	获取价格
ATF1508ASVL-20AU100	ATMEL	Highperformance EE PLD	获取价格
ATF1508ASVL-20JC84	ATMEL	Highperformance EE PLD	获取价格
ATF1508ASVL-20JI84	ATMEL	Highperformance EE PLD	获取价格
ATF1508ASVL-20JJ84	ATMEL	EE PLD, 20ns, PQCC84, PLASTIC, MS-018AF, LCC-84	获取价格
ATF1508ASVL-20JL84	ATMEL	EE PLD, 20ns, PQCC84, PLASTIC, MS-018AF, LCC-84	获取价格

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