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ATF1508AE-7CTI256 PDF预览

ATF1508AE-7CTI256

更新时间: 2024-02-26 21:11:06
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟ATM异步传输模式输入元件可编程逻辑
页数 文件大小 规格书
76页 633K
描述
EE PLD, 7.5ns, 128-Cell, PBGA256, 1 MM PITCH, TBGA-256

ATF1508AE-7CTI256 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:BGA, BGA256,16X16,40
针数:256Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.8
其他特性:YES最大时钟频率:133 MHz
系统内可编程:YESJESD-30 代码:S-PBGA-B256
JESD-609代码:e0JTAG BST:YES
专用输入次数:I/O 线路数量:96
宏单元数:128端子数量:256
最高工作温度:85 °C最低工作温度:-40 °C
组织:0 DEDICATED INPUTS, 96 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA256,16X16,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):225
电源:2.5/3.3,3.3 V可编程逻辑类型:EE PLD
传播延迟:7.5 ns认证状态:Not Qualified
子类别:Programmable Logic Devices最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30Base Number Matches:1

ATF1508AE-7CTI256 数据手册

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Features  
2nd Generation EE Complex Programmable Logic Devices  
– 3.0V to 3.6V Operating Range with 5V Tolerant I/Os  
– 32 - 512 Macrocells with Enhanced Features  
– Pin-compatible with Industry-standard Devices  
– Speeds to 4.5 ns Maximum Pin-to-pin Delay  
– Registered Operation to 225 MHz  
Enhanced Macrocells with Logic DoublingFeatures  
– Bury Either Register or COM while Using the Other for Output  
– Dual Independent Feedback Allows Multiple Latch Functions per Macrocell  
– 5 Product Terms per Macrocell, Expandable to 40 per Macrocell with Cascade  
Logic, Plus 15 More with Foldback Logic  
– D/T/Latch Configurable Flip-flops plus Transparent Latches  
– Global and/or per Macrocell Register Control Signals  
– Global and/or per Macrocell Output Enable  
– Programmable Output Slew Rate per Macrocell  
– Programmable Output Open Collector Option per Macrocell  
– Fast Registered Input from Product Term  
Enhanced Connectivity  
ATF15xxAE  
Family  
Datasheet  
ATF1502AE(L)  
ATF1504AE(L)  
ATF1508AE(L)  
ATF1516AE(L)  
ATF1532AE(L)  
– Single Level Switch Matrix for Maximum Routing Options  
– Up to 40 Inputs per Logic Block  
Advanced Power Management Features  
– ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and  
I/O for µA Level Standby Current on “Lversions  
– Pin-controlled 1 mA Standby Mode  
– Reduced-power Option per Macrocell  
– Automatic Power Down of Unused Macrocells  
– Programmable Pin-keeper Inputs and I/Os  
Available in Commercial and Industrial Temperature Ranges  
Available in All Popular Packages Including PLCC, PQFP, TQFP and BGA  
EE Technology  
– 100% Tested  
– Completely Reprogrammable  
– 10,000 Program/Erase Cycles  
Preliminary  
– 20 Year Data Retention  
– 2000V ESD Protection  
– 200 mA Latch-up Immunity  
JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993  
– Pull-up Option on JTAG Pins TMS and TDI  
IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG  
PCI-compliant  
Security Fuse Feature  
Rev. 2398G–PLD–09/02  

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