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ATF1502AS-10JC444 PDF预览

ATF1502AS-10JC444

更新时间： 2024-01-15 21:39:45
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
25页 318K
描述
High-performance EEPROM CPLD

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ATF1502AS-10JC444 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：LCC
包装说明：QCCJ,针数：44
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.8最大时钟频率：125 MHz
JESD-30 代码：S-PQCC-J44JESD-609代码：e0
长度：16.5862 mm湿度敏感等级：2
专用输入次数：I/O 线路数量：32
端子数量：44最高工作温度：70 °C
最低工作温度：组织：0 DEDICATED INPUTS, 32 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：225
可编程逻辑类型：EE PLD传播延迟：10 ns
认证状态：Not Qualified座面最大高度：4.57 mm
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：16.5862 mmBase Number Matches：1

ATF1502AS-10JC444 数据手册

 浏览型号ATF1502AS-10JC444的Datasheet PDF文件第1页浏览型号ATF1502AS-10JC444的Datasheet PDF文件第2页浏览型号ATF1502AS-10JC444的Datasheet PDF文件第3页浏览型号ATF1502AS-10JC444的Datasheet PDF文件第5页浏览型号ATF1502AS-10JC444的Datasheet PDF文件第6页浏览型号ATF1502AS-10JC444的Datasheet PDF文件第7页 
Figure 1. ATF1502AS Macrocell  
Product Terms and  
Select Mux  
Each ATF1502AS macrocell has five product terms. Each product term receives as its inputs  
all signals from both the global bus and regional bus.  
The product term select multiplexer (PTMUX) allocates the five product terms as needed to  
the macrocell logic gates and control signals. The PTMUX programming is determined by the  
design compiler, which selects the optimum macrocell configuration.  
OR/XOR/  
CASCADE Logic  
The ATF1502AS’s logic structure is designed to efficiently support all types of logic. Within a  
single macrocell, all the product terms can be routed to the OR gate, creating a 5-input  
AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be  
expanded to as many as 40 product terms with little additional delay.  
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-  
tions. One input to the XOR comes from the OR sum term. The other XOR input can be a  
product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows  
polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of  
product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.  
Flip-flop  
The ATF1502AS’s flip-flop has very flexible data and control functions. The data input can  
come from either the XOR gate, from a separate product term or directly from the I/O pin.  
Selecting the separate product term allows creation of a buried registered feedback within a  
combinatorial output macrocell. (This feature is automatically implemented by the fitter soft-  
ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-  
through latch. In this mode, data passes through when the clock is high and is latched when  
the clock is low.  
4
ATF1502AS(L)  
0995J–PLD–09/02  
1234567...25

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ATF1502AS-10JL44 ATMEL EE PLD, 10ns, PQCC44, PLASTIC, MS-018AC, LCC-44

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ATF1502AS-10JU44 ATMEL Highperformance EEPROM CPLD

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ATF1502AS-10QC44 ATMEL High Performance E2PROM CPLD

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