Datasheet > 驱动程序和接口 > 外围驱动器> ATA6832-PIQW

ATA6832-PIQW

更新时间： 2024-01-14 00:53:56

品牌	Logo	应用领域
爱特美尔 - ATMEL		外围驱动器驱动程序和接口接口集成电路异步传输模式 ATM
页数	文件大小	规格书
17页	331K
描述
High Temperature Triple Half-bridge Driver with SPI and PWM

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技术参数
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ATA6832-PIQW 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.68	Base Number Matches：	1

ATA6832-PIQW 数据手册

ATA6832

7. Noise and Surge Immunity

Parameters

Test Conditions

ISO 7637-1

Value

Conducted interferences

Interference suppression

ESD (Human Body Model)

CDM (Charge Device Model)

Level 4⁽¹⁾

Level 5

1.5 kV

500V

VDE 0879 Part 2

ESD S 5.1

ESD STM5.3.1

Note:

1. Test pulse 5: V_smax= 40V

8. Electrical Characteristics

7.5V < V_S< 40V; 4.75V < V_CC< 5.25V; INH = High; –40°C ≤ T_j≤ 200°C; T_a≤ 150°C; unless otherwise specified, all values refer to

GND pins.

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

Current Consumption

1.1

Quiescent current VS

V_VS< 20V, SI = low

10, 11

I_VS

µA

4.75V < V_VCC< 5.25V,

SI = low

1.2

1.3

1.4

Quiescent current VCC

I_VCC

160

V_VS< 20V normal

operating, all outputs

off, input register bit 13

(OLD) = high

Supply current VS

Supply current VCC

10, 11

I_VS

µA

4.75V < V_VCC< 5.25V,

normal operating

I_VCC

350

650

1.5

1.6

Discharge current VS

_VS= 32.5V, INH = low 10, 11

I_VS

0.5

2.0

5.5

_VS= 40V, INH = low

10, 11

Undervoltage Detection, Power-on Reset

Power-on reset

threshold

2.1

2.2

2.3

2.4

2.5

V_VCC

t_dPor

V_Uv

3.1

3.9

4.5

190

7.1

Power-on reset delay

After switching on V_CC

time

µs

Undervoltage-detection

V_CC= 5V

10, 11

5.5

threshold

Undervoltage-detection

V_CC= 5V

ΔV_Uv

t_dUV

0.6

hysteresis

Undervoltage-detection

delay time

µs

Thermal Prewarning and Shutdown

3.1

Thermal prewarning set

T_{jPW set}

170

155

195

180

220

205

°C

Thermal prewarning

reset

3.2

T_{jPW reset}

Thermal prewarning

hysteresis

3.3

3.4

ΔT_jPW

Thermal shutdown off

T_{j switch off}

200

225

250

°C

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of

final level. Device not in standby for t > 1 ms.

2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.

3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.

4951D–AUTO–08/09

1...6 7 8910 11 12...17

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