Datasheet > ATA6631-GAQW

ATA6631-GAQW

更新时间： 2024-02-22 18:14:33

品牌	Logo	应用领域
美国微芯 - MICROCHIP		电信光电二极管电信集成电路
页数	文件大小	规格书
26页	819K
描述
IC TXRX LIN SBC BUS 5V 8SOIC

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ATA6631-GAQW 技术参数

生命周期：	Transferred	包装说明：	SOP,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.82
JESD-30 代码：	R-PDSO-G8	长度：	4.9 mm
功能数量：	1	端子数量：	8
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
座面最大高度：	1.8 mm	标称供电电压：	13.5 V
表面贴装：	YES	电信集成电路类型：	INTERFACE CIRCUIT
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	3.9 mm

ATA6631-GAQW 数据手册

Functional Description

3.1

Physical Layer Compatibility

Since the LIN physical layer is independent from higher LIN layers (e.g., LIN protocol layer), all nodes with a LIN physical

layer according to revision 2.x can be mixed with LIN physical layer nodes, which are according to older versions (i.e., LIN

1.0, LIN 1.1, LIN 1.2, LIN 1.3) without any restrictions.

3.2

Supply Pin (VS)

LIN operating voltage is V_S= 5V to 27V. An undervoltage detection is implemented to disable transmission if V_Sfalls below

5V, in order to avoid false bus messages. After switching on V_S, the IC starts with the fail-safe mode and the voltage

regulator is switched on.

The supply current in sleep mode is typically 10µA and 35µA in silent mode.

3.3

3.4

Ground Pin (GND)

The IC does not affect the LIN bus in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of V_S.

Voltage Regulator Output Pin (VCC)

The internal 3.3V/5V voltage regulator is capable of driving loads up to 85mA, supplying the microcontroller and other ICs on

the PCB and is protected against overload by means of current limitation and overtemperature shut-down. Furthermore, the

output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold V_thun

3.5

3.6

Undervoltage Reset Output (NRES)

If the V_CCvoltage falls below the undervoltage detection threshold V_thun, NRES switches to low after tres_f

(Figure 6-1 on page 15). Even if V_CC= 0V the NRES stays low, because it is internally driven from the V_Svoltage. If V_S

voltage ramps down, NRES stays low until V_S< 1.5V and then becomes highly resistant.

The implemented undervoltage delay keeps NRES low for t_Reset= 4ms after V_CCreaches its nominal value.

Bus Pin (LIN)

A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to LIN

specification 2.x is implemented. The voltage range is from –27V to +40V. This pin exhibits no reverse current from the LIN

bus to V_S, even in the event of a GND shift or V_Battdisconnection. The LIN receiver thresholds are compatible with the LIN

protocol specification.

The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled.

3.7

3.8

Input/Output (TXD)

In normal mode the TXD pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to

ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is

turned off and the bus is in the recessive state. During fail-safe mode, this pin is used as output and is signalling the fail-safe

source.

Dominant Time-out Function (TXD)

The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in the

dominant state. If TXD is forced to low longer than t_DOM> 27ms, the LIN bus driver is switched to the recessive state.

Nevertheless, when switching to sleep mode, the actual level at the TXD pin is relevant.

To reactivate the LIN bus driver, switch TXD to high (> 10µs).

ATA6629/ATA6631 [DATASHEET]

9165E–AUTO–04/14

1 2 345 6 7...26

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