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ATA6630 PDF预览

ATA6630

更新时间: 2024-02-22 23:28:59
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
36页 1204K
描述
Negative Trigger Input for Watchdog

ATA6630 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:HVQCCN,
针数:20Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.63JESD-30 代码:S-XQCC-N20
长度:5 mm功能数量:1
端子数量:20封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE认证状态:Not Qualified
座面最大高度:1 mm标称供电电压:5 V
表面贴装:YES电信集成电路类型:ETHERNET TRANSCEIVER
端子形式:NO LEAD端子节距:0.65 mm
端子位置:QUAD宽度:5 mm
Base Number Matches:1

ATA6630 数据手册

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3. Functional Description  
3.1  
Physical Layer Compatibility  
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer),  
all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer  
nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without  
any restrictions.  
3.2  
Supply Pin (VS)  
The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to  
disable data transmission if VS falls below VSth in order to avoid false bus messages. After  
switching on VS, the IC starts in Fail-safe Mode, and the voltage regulator is switched on (i.e.,  
3.3V/5V/50 mA output capability).  
The supply current is typically 10 µA in Sleep Mode and 40 µA in Silent Mode.  
3.3  
3.4  
Ground Pin (GND)  
The ATA6628/ATA6630 does not affect the LIN Bus in the event of GND disconnection. It is able  
to handle a ground shift up to 11.5% of VS. The mandatory system ground is pin 5.  
Voltage Regulator Output Pin (VCC)  
The internal 3.3V/5V voltage regulator is capable of driving loads up to 50 mA. It is able to  
supply the microcontroller and other ICs on the PCB and is protected against overloads by  
means of current limitation and overtemperature shut-down. Furthermore, the output voltage is  
monitored and will cause a reset signal at the NRES output pin if it drops below a defined  
threshold Vthun. To boost up the maximum load current, an external NPN transistor may be used,  
with its base connected to the VCC pin and its emitter connected to PVCC.  
3.5  
3.6  
Voltage Regulator Sense Pin (PVCC)  
The PVCC is the sense input pin of the 3.3V/5V voltage regulator. For normal applications (i.e.,  
when only using the internal output transistor), this pin must be connected to the VCC pin. If an  
external boosting transistor is used, the PVCC pin must be connected to the output of this  
transistor, i.e., its emitter terminal.  
Bus Pin (LIN)  
A low-side driver with internal current limitation and thermal shutdown and an internal pull-up  
resistor compliant with the LIN 2.x specification are implemented. The allowed voltage range is  
between –27V and +40V. Reverse currents from the LIN bus to VS are suppressed, even in the  
event of GND shifts or battery disconnection. LIN receiver thresholds are compatible with the  
LIN protocol specification. The fall time from recessive to dominant bus state and the rise time  
from dominant to recessive bus state are slope controlled.  
4
ATA6628/ATA6630 [Preliminary]  
9117E–AUTO–07/10  

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