ATA6564
FIGURE 1-2:
SWITCHING FROM SILENT MODE TO NORMAL MODE
S
t
t
t
TXD
t
=
del(sil-norm)
10μs max
Operation
Mode
Silent Mode
Normal Mode
1.2.4
The
OVERTEMPERATURE
PROTECTION
1.2
Fail-Safe Features
1.2.1
TXD DOMINANT TIME-OUT
FUNCTION
output
drivers
are
protected
against
overtemperature conditions. If the junction temperature
exceeds the shutdown junction temperature, TJsd, the
output drivers are disabled until the junction
temperature drops below TJsd and pin TXD is at high
level again. This ensures that output driver oscillations
due to temperature drift are avoided. See Figure 1-3.
A TXD dominant time-out timer is started when the
TXD pin is set to low. If the low state on the TXD pin
persists for longer than tto(dom)TXD, the transmitter is
disabled, releasing the bus lines to recessive state.
This function prevents a hardware and/or software
application failure from driving the bus lines to a perma-
nent dominant state (blocking all network communica-
tions). The TXD dominant time-out timer is reset when
the TXD pin is set to high. If the low state on the TXD
pin was longer than tto(dom)TXD, then the TXD pin has
to be set to high longer 4 µs in order to reset the TXD
dominant time-out timer.
1.2.5
SHORT-CIRCUIT PROTECTION OF
THE BUS PINS
The CANH and CANL bus outputs are short-circuit pro-
tected, either against GND or a positive supply voltage.
A current-limiting circuit protects the transceiver
against damage. If the device is heating up due to a
continuous short on CANH or CANL, the internal
overtemperature protection switches off the bus
transmitter.
1.2.2
INTERNAL PULL-UP/PULL-DOWN
STRUCTURE AT THE TXD AND S
INPUT PINS
1.2.6
RXD RECESSIVE CLAMPING
The TXD pin has an internal pull-up resistor to VIO and
the S pin an internal pull-down resistor to GND. This
ensures a safe, defined state in case one or all of these
pins are left floating.
This fail-safe feature prevents the controller from
sending data on the bus if its RXD line is clamped to
HIGH (e.g., recessive). That is, if the RXD pin cannot
signalize a dominant bus condition because it is e.g,
shorted to VCC, the transmitter within ATA6564 is
disabled to avoid possible data collisions on the bus. In
Normal and Silent mode, the device permanently com-
pares the state of the high-speed comparator (HSC)
with the state of the RXD pin. If the HSC indicates a
dominant bus state for more than tRC_det without the
RXD pin doing the same, a recessive clamping situa-
tion is detected and the device is forced into Silent
mode. This Fail-safe mode is released by either
entering Unpowered mode or if the RXD pin is showing
a dominant (e.g., LOW) level again. See Figure 1-4.
1.2.3
UNDERVOLTAGE DETECTION ON
PINS VCC AND VIO
If VVCC or VVIO drop below their respective
undervoltage detection levels (Vuvd(VCC) and Vuvd(VIO)
(see Section , Electrical Characteristics), the
transceiver switches off and disengages from the bus
until VVCC and VVIO have recovered. The logic state of
the S pin is ignored until the VCC voltage or the VIO
voltage has recovered.
DS20005784D-page 4
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