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ATA555814-DDW

更新时间： 2024-02-10 23:32:20

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
42页	672K
描述
1 kbit R/W IDIC with Deterministic Anticollision

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技术参数
数据手册

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ATA555814-DDW 技术参数

生命周期：	Obsolete	包装说明：	DIE, DIE OR CHIP
Reach Compliance Code：	unknown	风险等级：	5.84
JESD-30 代码：	X-XUUC-N	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	DIE	封装等效代码：	DIE OR CHIP
封装形状：	UNSPECIFIED	封装形式：	UNCASED CHIP
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	NO LEAD
端子位置：	UPPER	uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT
Base Number Matches：	1

ATA555814-DDW 数据手册

The blocks 59, 60 and 61 contain Atmel’s manufacturer’s serial number (MSN). The top 4 digits

of block 61 specifiy the IC code of this product. The following byte of block 61 is fixed to E0h

which is the allocation class (ACL) for registered IC manufacturers as defined in TDR 15963-1;

followed by the manufacturer code (MFC), which compliant with ISO/IEC 7816-6/AM1, is defined

as 15h for Atmel. The remaining two blocks contain a 64-bit Atmel unique traceability code. The

data is divided in several sub-groups, a 36-bit lot ID code, a 5-bit wafer number and a 18-bit

sequential die number which represents the physical location of the chip on the processed wafer.

The ICR nibble (4 bits) of this manufacturer serial number (MSN) is used for the IC refer-

ence/version (ICR).

The unique tag identifier (Tag ID) blocks provide an address code with which each tag can be

individually identified and interrogated. These codes are programmed by either the tag system

administrator or the tag manufacturer into blocks 56 to 58. The allocation of individual Identifica-

tion codes must be handled so that an interrogator can never be confronted with two tags with

identical Tag IDs. This is an important issue as the Tag ID is used as the basis for accessing and

sorting tags during anticollision commands GetID, Select and SelectGroup.

The Atmel traceability code (blocks 60 and 59) itself provides a means of unique chip identifica-

tion so that this data content can be used as the Tag ID or a part of the Tag ID by copying it or

part of it into blocks 56 and 57.

The Tag ID code is located in blocks 56 to 58. It is MSB aligned so that it may occupy between

16 and 96 bits (see Figure 2-4 on page 5). This Tag ID length is set in the configuration block

(see Figure 2-7 on page 9) and has an impact on the time required to complete the anticollision

detection loop so it should be adjusted to suit system requirements. The default preprogrammed

Tag ID length is 64 bits. The anticollision algorithm is based on a bit by bit binary tree elimination,

carried out in parallel on all the Tag IDs within the interrogator field. This starts with the MSB of

the Tag ID (always in bit position 31 of block 56) and continues through to bit position

58 or until the Tag ID LSB, indicated by the configuration Tag ID length, is reached.

0 of block

2.7

Security Levels

The ATA5558 has three levels of security. Firstly, the restricted password access which pre-

vents unauthorized access to both user and system data but allows authorized access using the

correct password. Then a block orientated absolute write lock protection (lock bits) and finally

the Master Key with a security code which has to be set in the configuration block accordingly

(see Table 2-2 on page 8 and Figure 2-7 on page 9).

2.7.1

Password Protection

The user memory is subdivided into continuous page areas which can be configured so that

write or read/write and write operations on blocks within these pages can only be carried out

after the appropriate password has been transmitted to the tag (LoginRead or LoginWrite com-

mand). The read and write password protections are independent and user definable. The read

and write passwords are found in blocks 54 and 55 and the page security levels are defined in

the Page Security register of block 62 (see Figure 2-6 on page 7).

ATA5558 [Preliminary]

4681C–RFID–09/05

1...3 4 567 8 9...42

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ATA555814M01-DDT	ATMEL	1 kbit R/W IDIC with Deterministic Anticollision	获取价格
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ATA555814M01-PAE	ATMEL	1 kbit R/W IDIC with Deterministic Anticollision	获取价格
ATA555814M01-PP	ATMEL	1 kbit R/W IDIC with Deterministic Anticollision	获取价格
ATA555814-PAE	ATMEL	1 kbit R/W IDIC with Deterministic Anticollision	获取价格
ATA555814-PP	ATMEL	1 kbit R/W IDIC with Deterministic Anticollision	获取价格

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