Atmel ATA5551
8. Writing Data into the Atmel ATA5551
The write sequence of the Atmel® ATA5551 is shown below. Writing data into the transponder
occurs by interrupting the RF field with short gaps. After the start gap the standard write
OP code (10) is followed by the lock bit. The next 32 bits contain the actual data. The last three
bits denote the destination block address. If the correct number of bits have been received, the
actual data is programmed into the specified memory block.
Figure 8-1. Write Protocol
Standard OP-code
Address bits (e.g. block 4)
> 64 clocks
RF Field
32bit
1
0
0
1
0
0
Start gap
Lock bit
Write mode
Read mode
9. Write Data Decoding
The time elapsing between two detected gaps is used to encode the information. As soon as a
gap is detected, a counter starts counting the number of field clock cycles until the next gap is
detected. Depending on how many field clocks elapse, the data is regarded as “0” or “1”. The
required number of field clocks is shown in Figure 9-1. A valid “0” is assumed if the number of
counted clock periods is between 16 and 32, for a valid “1” it is 48 or 64 respectively. Any other
value being detected results in an error, and the device exits write mode and returns to read
mode.
Figure 9-1. Write Data Decoding Scheme
Field clock cycles
1
16
32
48
64
Write data decoder
fail
0
fail
1
writing done
10. Actual Behavior of the Device
The Atmel ATA5551 detects a gap if the voltage across the coils decreases below the threshold
value of an internal MOS transistor. Until then, the clock pulses are counted. The number given
for a valid “0” or “1” (see Figure 9-1) refers to the actual clock pulses counted by the device.
However, there are always more clock pulses being counted than were applied by the base
station. The reason for this is the fact that an RF field cannot be switched off immediately. The
coil voltage decreases exponentially. So although the RF field coming from the base station is
switched off, it takes some time until the voltage across the coils reaches the threshold value of
an internal MOS transistor and the device detects the gap.
Referring to the following diagram (see Figure 10-1 on page 8), this means that the device uses
the times t0 internal and t1 internal. The exact times for t0 and t1 are dependent on the application
(e.g., field strength, etc.).
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